View M58PR512LE_4228128.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58PR512LE M58PR001LE
512-Mbit or 1-Gbit (x 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories
Features
Supply voltage - VDD = 1.7 V to 2.0 V for program, erase and read - VDDQ = 1.7 V to 2.0 V for I/O buffers - VPP = 9 V for fast program Synchronous/asynchronous read - Synchronous burst read mode: 108 MHz, 66 MHz - Asynchronous page read mode - Random access: 96 ns Programming time - 4.2 s typical word program time using Buffer Enhanced Factory Program command Memory organization - Multiple bank memory array: 64 Mbit banks (512 Mb devices) 128 Mbit banks (1 Gb devices) - Four EFA (extended flash array) blocks of 64 Kbits Dual operations - Program/erase in one bank while read in others - No delay between read and write operations Block locking - All blocks locked at power-up - Any combination of blocks can be locked with zero latency - WP for block lock-down - Absolute Write protection with VPP = VSS
FBGA
TFBGA105 (ZAD) 9 x 11 mm TFBGA107 (ZAC) 8 x 11 mm
Security - 64 bit unique device number - 2112 bit user programmable OTP cells CFI (common flash interface) 100 000 program/erase cycles per block Electronic signature - Manufacturer code: 20h - 512 Mbit device: 8819 - 1 Gbit device: 880F ECOPACK(R) package available.

March 2008
Rev 4
1/123
www.numonyx.com 1
Contents
M58PR512LE, M58PR001LE
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Deep power-down (DPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 4.2 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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4.3 4.4 4.5 4.6 4.7 4.8 4.9
Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 29
4.9.1 4.9.2 4.9.3 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26
Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block Lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Set Enhanced Configuration Register command . . . . . . . . . . . . . . . . . . . 35 Read EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Program EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Erase EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Suspend EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Resume EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Lock EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Unlock EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Lock-down EFA Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5
Program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1 5.2 Program regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Program modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.1 5.2.2 Control program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Object program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3
Program methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Contents 5.3.1 5.3.2 5.3.3
M58PR512LE, M58PR001LE Single word program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Buffer program method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Buffer enhanced factory program method . . . . . . . . . . . . . . . . . . . . . . . 47
6
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Control program mode status bit (SR9) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Object program mode status bit (SR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 49 Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Erase status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Program Suspend Status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 51
7
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.1 7.2 7.3 7.4 7.5 Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 X latency bits (CR14-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8
Enhanced configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.1 8.2 8.3 Deep power-down mode bit (ECR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Deep power-down polarity bit (ECR14) . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Output driver control bits (ECR2-ECR0) . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 10
Extended flash array (EFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1 10.2 10.3 Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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11 12
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 63 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.1 12.2 12.3 12.4 12.5 Reading a block's lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 66
13 14 15 16 17
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 68 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Appendix B Common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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List of tables
M58PR512LE, M58PR001LE
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M58PR512LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M58PR001LE bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 EFA memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Factory Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program methods available with each program mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Relationships between program methods and program modes . . . . . . . . . . . . . . . . . . . . . 47 Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Enhanced configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Synchronous read AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Deep power-down AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, mechanical data . . . . . . . 88 Stacked TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 M58PR512LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 M58PR001LE - bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 M58PR512LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 M58PR001LE - block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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M58PR512LE, M58PR001LE Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56.
List of tables
Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Extended flash array bank and erase block region information . . . . . . . . . . . . . . . . . . . . 103 Extended flash array bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . 104 Command interface states - modify table, next state 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Command interface states - modify table, next state 2. . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Command interface states - modify table, next output 1 . . . . . . . . . . . . . . . . . . . . . . . . . 119 Command interface states - modify table, next output 2 . . . . . . . . . . . . . . . . . . . . . . . . . 120 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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List of figures
M58PR512LE, M58PR001LE
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TFBGA105 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TFBGA107 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Main array architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Program regions configured in control or object program mode. . . . . . . . . . . . . . . . . . . . . 45 X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Write AC waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Deep power-down AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Reset during deep power-down AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline. . . . . . . . 87 TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline. . . . . . . . 88 Program and EFA block program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 106 Buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . 108 Block erase and EFA block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 109 Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Main array and EFA locking operations flowchart and pseudocode . . . . . . . . . . . . . . . . . 111 Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 113 Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 114
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M58PR512LE, M58PR001LE
Description
1
Description
The M58PR512LE and M58PR001LE are 512 Mbit (32 Mbit x 16) and 1 Gbit (64 Mbit x 16) non-volatile flash memories. They are collectively referred to as the M58PRxxxLE in the rest of the document, unless otherwise specified. The M58PRxxxLE may be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up factory programming. The M58PRxxxLE has a uniform block architecture and is based on a multilevel cell technology:

The M58PR512LE has an array of 256 blocks, and is divided into 64 Mbit banks. There are 8 banks each containing 32 blocks of 128 KWords. The M58PR001LE has an array of 512 blocks, and is divided into 128 Mbit banks. There are 8 banks each containing 64 blocks of 128 KWords.
Each block contains 256 program regions of 1 Kbyte each, that are divided into 32 segments of 16 words. Each segment is split into two halves (A and B), according by the value on address input A3. The memory map is illustrated in Figure 4 and the main array architecture in Figure 5. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Table 2 and Table 3, and the memory maps are shown in Figure 4 and . Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 108 MHz. The device features an automatic standby mode and deep power-down mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven. The DPD (deep power-down) mode starts when the device is properly configured (ECR bit 15 is set) and the DPD signal is asserted. In DPD mode the device has the lowest power consumption.
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Description
M58PR512LE, M58PR001LE The M58PRxxxLE features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. In addition to the main memory array, the M58PRxxxLE features an extended flash array (EFA) divided into 4 blocks of 64 Kbits each. The EFA blocks are accessed through a separate set of commands. The operations available in the EFA blocks are asynchronous read (in non-page mode), single word program, erase and block locking. See Section 4: Command interface for details of the EFA commands set. See Table 4 for an extended flash array memory map. Table 18 and Table 19 describe the simultaneous operations allowed in the EFA blocks and the main memory array. The device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 OTP (one-time-programmable) protection registers of 128 bits each. The first protection register is divided into two areas: a 64-bit area containing a unique device number written by ST, and a 64-bit area one-time-programmable by the user. The user programmable area can be permanently protected. Figure 6, shows the Protection Register memory map. The memory is available in TFBGA105 or TFBGA107 packages, and is supplied with all the bits erased (set to '1'). Figure 1. Logic diagram
VDD VDDQ VPP 16 A0-Amax(1) W E G RP WP L K DPD M58PR512LE M58PR001LE WAIT DQ0-DQ15
VSS
VSSQ
AI12816c
1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.
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M58PR512LE, M58PR001LE
Description
Table 1.
Signal names
Function Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable Reset Write Protect Clock Latch Enable Wait Deep power-down Supply voltage Supply voltage for input/output buffers Optional supply voltage for fast program and erase Ground Ground input/output supply Do not use Not connected Inputs I/O Input Input Input Input Input Input Input Output Input Direction
Signal name A0-Amax(1) DQ0-DQ15 E G W RP WP K L WAIT DPD VDD VDDQ VPP VSS VSSQ DU NC
1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.
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Description Figure 2.
M58PR512LE, M58PR001LE TFBGA105 connections (top view through package)
1 2 3 4 5 6 7 8 9
A
DU
A4
A6
A7
A19
A23
A24
A25/ NC(1)
DU
B
A2
A3
A5
A17
A18
DPDF
A22
NC
A16
C
A1
VSS
VSS
VSS
NC
VSS
VSS
VSS
A15
D
A0
NC
NC
VDDF
LF
VDDF
NC
NC
A14
E
WPF
WF
NC
NC
NC
A21
A10
A13
F
NC
NC
NC
NC
NC
A20
A9
A12
G
NC
NC
EF
NC
NC
RPF
A8
A11
H
NC
NC
NC
NC
NC
NC
GF
NC
NC
J
VPPF
VDDQ
VDDQ
VDDF
NC
VDDF
VDDQ
VDDQ
WAITF
K
DQ2
VSS
VSS
VSS
KF
VSS
VSS
VSS
DQ13
L
DQ1
DQ3
DQ5
DQ6
DQ7
DQ9
DQ11
DQ12
DQ14
M
DU
DQ0
NC
DQ4
DQ8
DQ10
NC
DQ15
DU
AI109
1. Ball A8 is A25 in the M58PR0001LE and it is not connected internally (NC) in the M58PR512LE.
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M58PR512LE, M58PR001LE Figure 3.
1
Description
TFBGA107 connections (top view through package)
2 3 4 5 6 7 8 9
A
DU
NC
NC
NC
NC
DPDF
VSS
DU
B
DU
A4
A18
A19
VSS
VDDF
NC
A21
A11
C
NC
A5
NC
A23
VSS
NC
K
A22
A12
D
VSS
A3
A17
A24
VPPF
NC
NC
A9
A13
E
VSS
A2
A7
A25/ NC(1)
WPF
L
A20
A10
A15
F
NC
A1
A6
NC
RPF
WF
A8
A14
A16
G
VDDQ
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
NC
H
VSS
NC
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
NC
J
DU
NC
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
NC
EF
NC
NC
NC
NC
NC
VDDQ
NC
L
DU
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
NC
DU
DU
DU
DU
DU
DU
DU
AI11098d
1. Ball E4 is A25 in the M58PR0001LE and is not connected internally (NC) in the M58PR512LE.
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Description Table 2. M58PR512LE bank architecture
Number Bank 0 Bank 1 Bank 2 ---Bank size 64 Mbits 64 Mbits 64 Mbits ----
M58PR512LE, M58PR001LE
Blocks 32 blocks of 128 KWords 32 blocks of 128 KWords 32 blocks of 128 KWords ---32 blocks of 128 KWords Blocks 64 blocks of 128 KWords 64 blocks of 128 KWords 64 blocks of 128 KWords ---64 blocks of 128 KWords
Bank 7
64 Mbits
Table 3.
M58PR001LE bank architecture
Number Bank 0 Bank 1 Bank 2 ---Bank size 128 Mbits 128 Mbits 128 Mbits ---128 Mbits
Bank 7
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M58PR512LE, M58PR001LE Figure 4. Memory map
M58PR512LE Address lines A24-A0 0000000h 001FFFFh Bank 0 03E0000h 03FFFFFh 128 Kword 128 Kword 32 blocks
Description
1C00000h 1C1FFFFh Bank 7 1FE0000h 1FFFFFFh
128 Kword 32 blocks 128 Kword
M58PR001LE Address lines A25-A0 0000000h 001FFFFh Bank 0 07E0000h 07FFFFFh 128 Kword 128 Kword 64 blocks
3800000h 381FFFFh Bank 7 3FE0000h 3FFFFFFh
128 Kword 64 blocks 128 Kword
AI12817c
Table 4.
EFA memory map
Size 4 KWords (64 Kbits) 4 KWords (64 Kbits) 4 KWords (64 Kbits) 4 KWords (64 Kbits) Address range 0003000 - 0003FFF 0002000 - 0002FFF 0001000 - 0001FFF 0000000 - 0000FFF
EFA block 3 2 1 0
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Description Figure 5. Main array architecture
MAIN ARRAY 128 Kword block Bank 0
M58PR512LE, M58PR001LE
. . .
128 Kword block
BLOCK Program region 0 512 words Program region 1 512 words
PROGRAM REGION Segment 31 - 16 words Segment 30 - 16 words
. . . . . .
Program region 254 512 words Program region 255 512 words
. . .
Segment 2 - 16 words Segment 1 - 16 words Segment 0 - 16 words
128 Kword block Bank 7
. . .
128 Kword block 512 Mbits or 1 Gbits
ai12886b
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M58PR512LE, M58PR001LE
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device.
2.1
Address inputs (A0-Amax)
Amax is the highest order address input. Amax is A24 in the M58PR512LE and A25 in the M58PR001LE. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller.
2.2
Data inputs/outputs (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation.
2.3
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level.
2.4
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
2.5
Write Enable (W)
The Write Enable input controls the bus write operation of the memory's command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first.
2.6
Write Protect (WP)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked (refer to Table 21: Lock status).
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Signal descriptions
M58PR512LE, M58PR001LE
2.7
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode, this means the outputs are high impedance and the current consumption is reduced to the reset supply current IDD2. Refer to Table 26: DC characteristics - currents for the value of IDD2. After Reset, all blocks are in the locked state and the configuration register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be tied to VRPH (refer to Table 27: DC characteristics - voltages).
2.8
Deep power-down (DPD)
The deep power-down input is used to put the device in deep power-down mode. When the device is in standby mode and the enhanced configuration register bit ECR15 is set, asserting the deep power-down input will cause the memory to enter the deep powerdown mode. When the device is in the deep power-down mode, the memory cannot be modified and the data is protected. The polarity of the DPD pin is determined by ECR14. The deep power-down input is active Low by default.
2.9
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.10
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.11
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
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M58PR512LE, M58PR001LE
Signal descriptions
2.12
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).
2.13
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. VDDQ is sampled at the beginning of program/erase operations. If VDDQ is lower than VLKOQ, the device is reset.
2.14
VPP program supply voltage
VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0 V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 26 and 27, DC characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the program/erase algorithm is completed.
2.15
VSS ground
VSS ground is the reference for the core supply. It must be connected to the system ground.
2.16
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS.
Note:
Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 11: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents.
19/123
Bus operations
M58PR512LE, M58PR001LE
3
Bus operations
There are seven standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby, Reset and deep power-down. See Table 5: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus write operations.
3.1
Bus Read
Bus Read operations are used to output the contents of the memory array, the Electronic signature, the status register and the common flash interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Section 4: Command interface). See figures 12, 13, 14 and 15, Read AC waveforms, and tables 28 and 29, Read AC characteristics, for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write commands to the memory or latch input data to be programmed. A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the Write operation by toggling Latch Enable. In this case the Latch Enable should be tied to VIH during the Bus Write operation. See figures 17 and 18, Write AC waveforms, and tables 30 and 31, Write AC characteristics, for details of the timing requirements.
3.3
Address Latch
Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must be at VIL during Address Latch operations. The addresses are latched on the rising edge of Latch Enable.
3.4
Output Disable
The outputs are high impedance when the Output Enable is at VIH.
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M58PR512LE, M58PR001LE
Bus operations
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.
3.6
Reset
During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
3.7
Deep power-down (DPD)
The memory enters the deep power-down mode from the Standby mode (RP and E are deasserted, VIH) by setting ECR15 High (set to `1') and asserting the DPD pin (these two events can be done in any order). The DPD pin polarity is determined by the value of ECR14 when:

ECR14 is cleared (`0') the DPD pin is active Low. The DPD pin is active Low by default. ECR14 is set (`1'), the DPD pin is active High. Values of the configuration register, enhanced configuration register, block lock bits, and bank states are preserved. Status register is reset to 80h.
While in DPD mode, the:

If the status register contains errors before entering the DPD mode, the error bits are lost after exiting DPD mode. The device should not be put in deep power-down mode while a program, erase or suspend operation is in progress, otherwise the operation aborts, and the memory contents are no longer valid. The deep power-down mode is exited tDPHEL after de-asserting the DPD pin. Upon exiting the deep power-down mode, the memory reverts to standby mode. If the RP pin is asserted while in DPD mode, the device exits DPD mode after tPHEL and ECR15 is reset to 0.
21/123
Bus operations Table 5. Bus operations(1)
E VIL VIL VIL VIL VIH X VIH G VIL VIH X VIH X X X W VIH VIL VIH VIH X X X L VIL(4) VIL(4) VIL X X X X RP VIH VIH VIH VIH VIH VIL VIH DPD(2) Deasserted(5) Deasserted(5) Deasserted(5) Deasserted(5) Deasserted(5) Deasserted(5) Asserted(7)
M58PR512LE, M58PR001LE
Operation Bus read Bus write Address latch Output disable Standby Reset Deep powerdown
1. X = Don't care.
WAIT(3)
DQ15-DQ0 Data output Data input Data output or Hi-Z(6)
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
2. The DPD signal polarity depends on the value of the ECR14 bit. 3. WAIT signal polarity is configured using the Set Configuration Register command. 4. L can be tied to VIH if the valid address has been previously latched. 5. If ECR15 is set to '0', the device cannot enter the deep power-down mode, even if DPD is asserted. 6. Depends on G. 7. ECR15 has to be set to `1' for the device to enter deep power-down.
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M58PR512LE, M58PR001LE
Command interface
4
Command interface
All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a status register, whose output may be read at any time to monitor the progress or the result of the operation. The command interface is reset to read mode when power is first applied, when exiting from Reset, or whenever VDD is lower than VLKO. Command sequences must be followed precisely. Any invalid combination of commands are ignored. Refer to Table 6: Command codes, Table 7: Standard commands, Table 8: Factory Program command for a summary of the command interface. Table 6.
Hex code 01h 03h 04h 20h 24h 2Fh 41h 44h 50h 60h 64h 70h 80h 90h 94h 98h B0h BCh C0h D0h E9h FFh
Command codes
Command Block Lock Confirm and EFA Block Lock Confirm Set Configuration Register Confirm Set Enhanced Configuration Register Confirm Block Erase Setup EFA Block Erase Setup Block Lock-down Confirm and EFA Block Lock-down Confirm Program Setup EFA Program Setup Clear Status Register Block Lock Setup, Block Unlock Setup, Block Lock-down Setup, Set Configuration Register Setup and Enhanced Configuration Register Setup EFA Block Lock, EFA Block Lock-down, EFA Block Unlock Read Status Register Buffer Enhanced Factory Program Read Electronic Signature Read EFA Read CFI query Program/Erase Suspend Blank Check Setup Protection Register Program Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm or Buffer Program Confirm, Buffer Enhanced Factory Program Confirm, Blank Check Confirm, Unlock EFA Block Confirm, EFA Block Erase Confirm Buffer Program Read Array
23/123
Command interface
M58PR512LE, M58PR001LE
4.1
Read Array command
The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations output the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues. However, the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected.
4.2
Read Status Register command
The device contains a status register that monitors program or erase operations. The Read Status Register command reads the contents of the status register for the addressed bank. One bus write cycle is required to issue the Read Status Register command. Once a bank is in read status register mode, subsequent read operations output the contents of the status register. The status register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the status register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the status register. A Read Array command is required to return the bank to read array mode. See Table 13 for the description of the status register bits.
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Command interface
4.3
Read Electronic Signature command
The Read Electronic Signature command reads the manufacturer and device codes, the lock status of the addressed bank, the Protection Register, the configuration register, and the enhanced configuration register. One bus write cycle is required to issue the Read Electronic Signature command. Once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the Protection Register, the configuration register, or the enhanced configuration register (see Table 9). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during protection register program operations. Dual operations between the EFA and the electronic signature locations are not allowed (see Table 20: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation the bank goes into read electronic signature mode. Subsequent bus read cycles output the electronic signature data and the Program/Erase Controller continues to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the electronic signature. A Read Array command is required to return the bank to read array mode.
4.4
Read CFI Query command
The Read CFI Query command is used to read data from the CFI (common flash interface). One bus write cycle is required to issue the Read CFI Query command. Once a bank is in read CFI query mode, subsequent bus read operations in the same bank output the contents of the CFI. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank goes into read CFI query mode. Subsequent bus read cycles output the CFI data and the Program/Erase Controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read from the CFI. A Read Array command is required to return the bank to read array mode. Dual operations between the EFA and the CFI memory space are not allowed (see Table 20: Dual operation limitations for details).
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4.5
Clear Status Register command
The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, SR3, SR4, SR5, SR8 and SR9) in the status register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the status register do not automatically return to `0' when a new command is issued. The error bits in the status register should be cleared before attempting a new program or erase command.
4.6
Block Erase command
The Block Erase command erases a block. It sets all the bits within the selected block to '1', and all previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block is not changed, and the status register outputs the error. Two bus write cycles are required to issue the command.

The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the block erase confirm code, status register bits SR4 and SR5 are set and the command is aborted. Once the command is issued, the bank enters read status register mode and any read operation within the addressed bank outputs the contents of the status register. A Read Array command is required to return the bank to read array mode. During block erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command; all other commands are ignored. The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are provided in Table 22: Program/erase times and endurance cycles. See Appendix C, Figure 27: Block erase and EFA block erase flowchart and pseudocode for a suggested flowchart for using the Block Erase command.
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Command interface
4.7
Program command
The Program command programs a single word to the memory array. It is supported only by program regions configured in control program mode. If a Program command is issued to a program region configured in object program mode, the program operation is aborted and the SR4 and SR8 status register bits are set (see Section 5: Program operations). Two bus write cycles are required to issue the Program command.

The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the P/EC (Program/Erase Controller).
The Program command has to be written to the 'A' segment halves (address bit A3 = 0) in the 1 Kbyte program region, whereas the data to be programmed is written to the specific address of the bank to be programmed. Once the programming has started, read operations in the bank being programmed output the status register contents. Programming can be performed in one bank at a time, meanwhile the other banks must be in Read or Erase Suspend mode. The status register P/EC bit, SR7, indicates the progress of the program operation. It should be read to check whether the operation has completed or not. After completion of the program operation (SR7 = 1), one of the error bits (SR4, SR3 and SR1) going High means that an error was detecte. Either a failure occurred during programming, VPP is outside the allowed voltage range, or an attempt to program a locked block was made. See Section 6: Status register for detailed information. During a program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command; all other commands are ignored. A Read Array command is required to return the bank to read array mode. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. Typical program times are given in Table 22: Program/erase times and endurance cycles. The program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 24: Program and EFA block program flowchart and pseudocode for the flowchart for using the Program command.
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4.8
Buffer Program command
The Buffer Program command uses the device's 1 Kbyte write buffer to speed up programming. Up to 1 Kbyte can be loaded into the write buffer and programmed into the specified 1 Kb aligned location in the main array. The Buffer Program command dramatically reduces in-system programming time compared to the standard non-buffered program command. The Buffer Program command is supported in both object program mode and control program mode. When using the Buffer Program command in a region configured in object mode, the start programming address must be aligned to the 1 Kb buffer. When using the Buffer Program command in a region configured in control program mode, the programmed address must be within the 'A' segment halves of the program region (addresses with A3 = 0) and the 'B' segment halves of the program region (addresses with A3 = 1) must be filled only with FFFFh data. Before issuing the Buffer Program Setup command, the status register bit SR7 at the bank address should be read to ensure that the buffer is available (SR7=1). Four successive steps are required to issue the Buffer Program command: 1. 2. The first bus write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. The second bus write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. The maximum buffer count is 1FF (512 words). Use n+1 bus write cycles to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. The start address must be aligned to a 1 Kb boundary. The final bus write cycle confirms the Buffer Program command and starts the program operation.
3.
4.
All the addresses used in the buffer program operation must lie within the same block. The buffer program operation does not change the read status of the banks until the Buffer Program Confirm command is issued. The Buffer Program Confirm command changes the read status of the bank to read status register, therefore, after the Buffer Program Confirm command, read operations in the bank output the contents of the status register. Invalid address combinations or failure to follow the correct sequence of bus write cycles sets an error in the status register and aborts the operation without affecting the data in the memory array. If the block being programmed is protected, an error is set in the status register and the operation aborts without affecting the data in the memory array. During buffer program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. Refer to Chapter 11 for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 25: Buffer program flowchart and pseudocode for a suggested flowchart on using the Buffer Program command.
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Command interface
4.9
Buffer Enhanced Factory Program command
The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where programming time is critical. This command programs one or more write buffer(s) of 1 Kb to an aligned 1 Kb program region. Once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same main array block. Only one block can be programmed at a time. When programming a program region configured in control program mode with the Buffer Enhanced Factory Program command, the 'B' half segment addresses (A3 = 1) should not contain '0' values. When writing to a program region configured in object program mode, the B half may contain some '0' values. If the number of bytes to program is less than 1 Kbyte, the remaining addresses must be filled with FFFFh. The use of the Buffer Enhanced Factory Program command requires the following operating conditions:

VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30 C 10 C The targeted block must be unlocked The start address must be aligned with the start of a 1 Kb buffer boundary The address must remain the start address throughout programming.
Dual operations are not supported during the Buffer Enhanced Factory Program operation, and the command cannot be suspended. The Buffer Enhanced Factory command programs one block at a time. All data to be programmed must be contained in a single block. If the internal address counter is incremented beyond the highest block address, addressing wraps around to the beginning of the block. The Buffer Enhanced Factory Program command consists of three phases: the setup phase, the program and verify phase, and the exit phase (please refer to Table 8: Factory Program command for detailed information).
4.9.1
Setup phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command.

The first bus write cycle sets up the Buffer Enhanced Factory Program command. The second bus write cycle confirms the command.
After the confirm command is issued, read operations output the contents of the status register. The Read Status Register command must not be issued or it is interpreted as data to program. The status register P/EC bit SR7 should be read to check that the P/EC is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the buffer enhanced factory program operation is terminated. See Chapter 6: Status register for details on the error.
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4.9.2
Program and verify phase
The program and verify phase requires 512 cycles to program the 512 words to the write buffer. The data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (512 words). To program less than 512 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the program and verify phase of the command. 1. Use one bus write operation to latch the start address and the first word to be programmed. The status register bank write status bit SR0 should be read to check that the P/EC is ready for the next word. Each subsequent word to be programmed is latched with a new bus write operation. The address must remain the start address as the P/EC increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. status register bit SR0 should be read between each bus write cycle to check the P/EC is ready for the next word. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary.
2.
3.
The program and verify phase can be repeated, without re-issuing the command, to program additional 512 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block have been programmed, write FFFFh to any address outside the block containing the start address to terminate the program and verify phase.
Status register bit SR0 must be checked to determine whether the program operation is finished. The status register may be checked for errors at any time but it must be checked after the entire block has been programmed.
4.9.3
Exit phase
When status register P/EC bit SR7 is set to `1' this indicates that the device has exited the buffer enhanced factory program operation. Upon exiting the buffered enhanced factory program algorithm by writing FFFFh to an address outside the block containing the start address, the Read mode of the programmed and addressed banks remains unchanged. A full status register check should be done to ensure that the block has been successfully programmed. See Chapter 6: Status register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are provided in Table 22. See Appendix C, Figure 32: Buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the Buffer Enhanced Factory Program command.
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Command interface
4.10
Program/Erase Suspend command
The Program/Erase Suspend command pauses a program or block erase operation. The command can be addressed to any bank and is required to restart a suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the status register are set to `1'. The following commands are accepted during Program/Erase Suspend: - - - - - - - Program/Erase Resume Read Array (data from erase-suspended block or program-suspended word is not valid) Read Status Register Read Electronic Signature Read CFI Query Read EFA Clear Status Register
Additionally, if the suspended operation is a block erase then the following commands are also accepted: - - - - - - - Set Configuration Register Program (except in erase-suspended block) Buffer Program (except in erase-suspended blocks) Block Lock Block Lock-Down Block Unlock Program EFA
During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-down commands. When the Program/Erase Resume command is issued the operation completes. It is possible to accumulate multiple suspend operations. For example, it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. If a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read EFA, Read Status Register, Read Electronic Signature or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. Refer to Chapter 11 for detailed information about simultaneous operations allowed during program/erase suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Suspend command.
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4.11
Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended by the Program/Erase Suspend command. One bus write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in read status register, read electronic signature or read CFI query mode, the bank remains in that mode and outputs the corresponding data. If a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation is complete. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Resume command.
4.12
Protection Register Program command
The Protection Register Program command programs the user OTP area of the Protection Register and the two Protection Register Locks. The device features 16 OTP areas of 128 bits and one OTP area of 64 bits, as shown in Figure 6: Protection Register memory map. The areas are programmed one word at a time. When shipped, all bits in the area are set to `1'. Only the user can program the bits to `0'. Two bus write cycles are required to issue the Protection Register Program command.

The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller.
Read operations to the bank being programmed output the status register content after the program operation has started. Attempting to program a previously-protected Protection Register results in a status register error. The Protection Register Program cannot be suspended. Dual operations between the EFA and the Protection Register memory space are not allowed (see Table 20: Dual operation limitations for details). The two Protection Register locks are used to protect the OTP areas from further modification. The protection of the OTP areas is not reversible. Refer to Figure 6: Protection Register memory map for details on the lock bits. See Appendix C, Figure 31: Protection Register program flowchart and pseudocode for a flowchart for using the Protection Register Program command.
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Command interface
4.13
Set Configuration Register command
The Set Configuration Register command writes a new value to the configuration register. Two bus write cycles are required to issue the Set Configuration Register command.

The first cycle sets up the Set Configuration Register command and the address corresponding to the configuration register content. The second cycle writes the configuration register data and the confirm command.
The configuration register data must be written as an address during the bus write cycles, such as A0 = CR0, A1 = CR1, ..., A15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the configuration register.
4.14
Block Lock command
The Block Lock command is used to lock a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two bus write cycles are required to issue the Block Lock command.

The first bus cycle sets up the Block Lock command. The second bus write cycle latches the block address and locks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 21 shows the lock status after issuing a Block Lock command. Once set, the block lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command. Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock command.
4.15
Block Unlock command
The Block Unlock command unlocks a block, allowing the block to be programmed or erased. Two bus write cycles are required to issue the Block Unlock command.

The first bus cycle sets up the Block Unlock command. The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Table 21 shows the protection status after issuing a Block Unlock command. Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Block Unlock command.
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4.16
Block Lock-down command
The Block Lock-down command locks down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two bus write cycles are required to issue the Block Lock-down command.

The first bus cycle sets up the Block Lock-down command. The second bus write cycle latches the block address and locks-down the block.
The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 21 shows the Lock Status after issuing a Block Lock-down command. Refer to Section 12: Block locking for a detailed explanation and Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock-down command.
4.17
Blank Check command
The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. Two bus cycles are required to issue the Blank Check command: The first bus cycle writes the Blank Check command to any address in the block to be checked. The second bus cycle writes the Blank Check Confirm command (D0h) to any address in the block to be checked and starts the blank check operation. If the second bus cycle is not Blank Check Confirm, status register bits SR4 and SR5 are set to `1' and the command aborts. Once the command is issued the addressed bank automatically enters the status register mode and further reads within the bank output the status register contents. The only operation permitted during blank check is read status register. Dual operations are not supported while a blank check operation is in progress. Blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. The SR7 status register bit indicates the status of the blank check operation in progress: SR7 = `0' means that the blank check operation is still ongoing. SR7 = `1' means that the operation is complete. The SR5 status register bit goes High (SR5 = `1') to indicate that a blank check operation has failed. At the end of the operation the bank remains in the Read status register mode until another command is written to the command interface. See Appendix C, Figure 30: Blank check flowchart and pseudocode for a suggested flowchart for using the Blank Check command. Typical Blank Check times are provided in Table 22: Program/erase times and endurance cycles.
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Command interface
4.18
Set Enhanced Configuration Register command
The Set Enhanced Configuration Register command is used to write a new value to the enhanced configuration register. Two bus write cycles are required to issue the Set Enhanced Configuration Register command.

The first cycle sets up the Set Enhanced Configuration Register command and the address corresponding to the enhanced configuration register contents. The second cycle writes the enhanced configuration register data and the Confirm command.
The enhanced configuration register data must be written as an address during the bus write cycle, such as A0 = ECR0, A1 = ECR1, ..., A15 = ECR15. If the Set Enhanced Configuration Register setup write cycle is not followed by the Set Enhanced Configuration Register Confirm command (04h), status register bits SR4 and SR5 are set. After successfully executing this command, the bank addressed returns to read array state.
4.19
Read EFA Block command
The Read EFA Block command places the addressed bank in the read EFA mode, where all addresses in the addressed bank are remapped to EFA block addresses. When the device is in read EFA mode, the main array blocks in the addressed bank can no longer be accessed until a Read Array command is issued to the bank. One bus write cycle is required to issue the Read EFA Block command. Once a bank is in read EFA mode, subsequent read operations from any address within the EFA block output the EFA data from the EFA block. See Table 4: EFA memory map for details. EFA blocks can be read through asynchronous or single synchronous read operations only. The Asynchronous page read mode cannot be used to read the EFA blocks. If a Read EFA command is issued in a bank that is programming or erasing, the read mode of the bank changes to Read EFA mode.
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4.20
Program EFA Block command
The Program EFA Block command programs a single word to an EFA block. Two bus write cycles are required to issue the Program EFA Block command. The first bus cycle sets up the Program EFA Block command. The second cycle latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the status register contents. Issuing the Program EFA Block command to an address outside the EFA block address range generates a Program Error in the status register (SR4=1). A Read EFA Block command is required to return the bank to Read EFA mode. Refer to Section 11 for detailed information about simultaneous operations allowed in the banks not being programmed. Typical EFA Program times are given in Table 22: Program/erase times and endurance cycles. The program operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed when a program EFA block operation is aborted, the word must be reprogrammed. See Appendix C, Figure 24: Program and EFA block program flowchart and pseudocode for the flowchart for using the Program EFA Block command.
4.21
Erase EFA Block command
The Erase EFA Block command erases an EFA block. It sets all the bits within the selected block to '1', and all previous data in the block is lost. If the EFA block is protected, then the erase operation aborts, the data in the EFA block is not changed, and the status register outputs the error. Two bus write cycles are required to issue the command.

The first bus cycle sets up the Erase EFA Block command. The second latches the EFA block address and starts the Program/Erase Controller.
The first cycle brings the EFA plane to the foreground and latches the address of the EFA block to be erased. Reading from the bank when the EFA plane is in the foreground returns the status register. Once the Erase operation has started, read operations in the bank being erased output the status register contents. If the Erase EFA Block Confirm command code is not issued in the second bus cycle, status register bits SR4 and SR5 are set, the command is aborted, and the addressed bank remains in the read status register mode. Issuing the Erase EFA Block command outside the EFA block address range generates an error in the status register (SR5=1). The erase EFA block operation aborts if Reset, RP, is at VIL. As data integrity cannot be guaranteed when the erase EFA block operation is aborted, the block must be erased again. Refer to Section 11: Dual operations and multiple bank architecture section for detailed information about simultaneous operations allowed with array and non-array blocks. Typical erase times are provided in Table 22: Program/erase times and endurance cycles. See Appendix C, Figure 27: Block erase and EFA block erase flowchart and pseudocode for a suggested flowchart for using the Erase EFA Block command.
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Command interface
4.22
Suspend EFA Block command
The Suspend EFA Block command pauses a program or erase EFA block operation. The command can be addressed to any bank. The Resume EFA Block command is required to restart the suspended operation. One bus write cycle is required to issue the Suspend EFA Block command. Once the Program/Erase Controller has paused, bits SR7, SR6 and/ or SR2 of the status register are set to '1'. The following commands are accepted during Suspend EFA Block: - - - - - - - Resume EFA Block Read Array Read EFA Block (data from erase-suspended blocks or program-suspended words is not valid) Read Status Register Read Electronic Signature Read CFI Query. Clear Status Register
Additionally, if the suspended operation was an erase EFA block operation then the following commands are also accepted: - - - - - - - - - Set Configuration Register Program EFA Block (except in the erase-suspended block) Program and Buffer Program in the main array Block Lock Block Lock-down Block Unlock EFA Block Lock EFA Block Lock-down EFA Block Unlock
During Suspend EFA Block the EFA block being erased can be protected by issuing the EFA Block Lock or EFA Block Lock-down commands. When the Resume EFA Block command is issued, the operation is resumed and completes. The suspend EFA block operation can be repeated. For example, it is possible to suspend an erase EFA block operation, to start a program EFA block operation, to suspend the program operation, and then read EFA locations. If a Program EFA Block command is issued during a suspend EFA block operation, the erase EFA block operation cannot be resumed until the program operation has completed. The state of the bank where the command was issued do not change. Refer to Section 11 for detailed information about simultaneous operations allowed during a suspend EFA block operation.
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During a suspend EFA block operation, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, is VIL. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Suspend EFA Block command.
4.23
Resume EFA Block command
The Resume EFA Block command restarts the program or erase EFA block operation suspended by the Suspend EFA Block command. One bus write cycle is required to issue the command. The command can be issued to any address. The Resume EFA Block command does not change the read mode of the banks. If a Program EFA Block command is issued while an erase EFA block operation has been suspended, then the erase operation cannot be resumed until the program operation has completed. See Appendix C, Figure 26: Program suspend and resume flowchart and pseudocode and Figure 28: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Resume EFA Block command.
4.24
Lock EFA Block command
The Lock EFA Block command is used to lock an EFA block and prevent program or erase operations from changing the data in it. All EFA blocks are locked after power-up or reset. Two bus write cycles are required to issue the Lock EFA Block command.

The first bus cycle sets up the Lock EFA Block command. The second bus cycle latches the Block address and locks the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature command. Once set, the block lock bits remain set even after a hardware reset or a power-down/ power-up sequence. They are cleared by an Unlock EFA Block command. Program or erase operations to a locked EFA block generates an error in the status register (SR1=1). Refer to Section 12: Block locking for a detailed explanation. See Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock EFA Block command.
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Command interface
4.25
Unlock EFA Block command
The Unlock EFA Block command unlocks an EFA block, allowing the EFA block to be programmed or erased. Two bus write cycles are required to issue the Unlock EFA Block command.

The first bus cycle sets up the Unlock EFA Block command. The second bus write cycle latches the block address and unlocks the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature command. Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Unlock EFA Block command.
4.26
Lock-down EFA Block command
The Lock-down EFA Block command locks down a locked or unlocked EFA block. A locked-down EFA block cannot be programmed or erased. The lock status of a lockeddown EFA block cannot be changed when WP is Low, VIL. When WP is High, VIH, the lockdown function is disabled and the locked EFA blocks can be individually unlocked by issuing the Unlock EFA Block command. Two bus write cycles are required to issue the Lock-down EFA Block command.

The first bus cycle sets up the Lock-down EFA Block command. The second bus write cycle latches the block address and locks down the block.
The lock status can be monitored for each EFA block using the Read Electronic Signature command. Locked-down EFA blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 21 shows the lock status after issuing a Lock-down EFA Block command. Refer to Section 12: Block locking for a detailed explanation and to Appendix C, Figure 29: Main array and EFA locking operations flowchart and pseudocode for a flowchart for using the Lock-down EFA Block command.
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Command interface Table 7. Standard commands
M58PR512LE, M58PR001LE
Bus operations(1) Commands Cycles 1st cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 n+4
(4)
2nd cycle Data FFh 70h 90h 98h 50h 20h 41h E9h PD1 PDn+1 B0h D0h C0h 60h Write Write Write Write Write Write Write Read Write Write PRA CRD BA ECRD BA BA BA WA WA BA PRD 03h 01h 04h D0h 2Fh D0h RD PD D0h Write Write Write Write Write BA WA BA PA2 X D0h PD n PD2 D0h Op. Read Read Read Read Add WA BKA(2) BKA
(2)
Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3)
Data RD SRD ESD QD
Write Write Write Write Write Write Write Write
BKA(2)
BA PA1 PAn+1 X X PRA CRD BKA or BA ECRD BKA or BA(3) BKA or BA BA BKA BKA or WA BKA or BA X X BKA or BA BKA or
(3) (3) (3) (3)
Buffer Program
Write Write
Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Set Enhanced Configuration Register Block Unlock Block Lock-down Blank Check Read EFA Block Program EFA Block Erase EFA Block Suspend EFA Block Resume EFA Block Lock EFA Block Unlock EFA Block Lock-down EFA Block
1 1 2 2 2 2 2 2 2 1+ 2 2 1 1 2 2 2
Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
60h 60h 60h 60h BCh 94h 44h 24h B0h D0h 64h 64h 64h
(3)
Write Write Write
BA BA BA
01h D0h 2Fh
BA(3)
BA
1. X = Don't care, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PA = Program Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = configuration register Data, ECRD = enhanced configuration register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 9. 3. Any address within the bank can be used. 4. n+1 is the number of words to be programmed.
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M58PR512LE, M58PR001LE Table 8. Factory Program command(1)
Bus write operations Cycles Command Phase 1st Add Setup 2 Buffer Enhanced Program/ Verify(3) 512 Factory Program Exit 1 BKA or WA(2) WA1 Data 80h PD1 2nd 3rd Data
Command interface
Final -1 Add Data
Final Add Data
Add Data Add WA1 WA1 D0h PD2 WA1
PD3
WA1 PD511 WA1 PD512
NOT FFFFh BA1(4)
1. WA = Word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = Don't care. 2. Any address within the bank can be used. 3. The program/verify phase can be executed any number of times as long as the data is programmed to the same block. 4. WA1 is the start address, NOT BA1 = Not Block Address of WA1.
Table 9.
Electronic signature codes
Code Address (h) Bank address + 00 512 Mbit 1 Gbit Locked Main block Unlocked Locked and Locked-down Unlocked and Locked-down Locked EFA block Unlocked Locked and Locked-down Unlocked and Locked-down Block address + 02 Bank address + 01 Data (h) 0020 8819 880F DQ1, DQ0 = 01 DQ1, DQ0 = 00 DQ1, DQ0 = 11 DQ1, DQ0 = 10 DQ5, DQ4 = 01 DQ5, DQ4 = 00 DQ5, DQ4 = 11 DQ5, DQ4 = 10 Bank address + 05 Bank address + 06 ST factory default OTP area permanently locked Bank address + 80 Bank address + 81 CR(1) ECR(1) 0002 0000 Unique device number
Manufacturer code Device code
Block protection
Configuration register Enhanced configuration register Protection Register PR0 Lock
Protection Register PR0
Bank address + 84 Bank address + 85 Bank address + 88
OTP area PRLD(1) OTP area
Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16
Bank address + 89 Bank address + 8A Bank address + 109
1. CR = configuration register, ECR = enhanced configuration register, PRLD = Protection Register Lock Data.
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Command interface Figure 6. Protection Register memory map
PROTECTION REGISTERS 109h PR16
M58PR512LE, M58PR001LE
User Programmable OTP 102h
91h
PR1
User Programmable OTP
8Ah 89h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
88h 85h 84h
PR0 User Programmable OTP
Unique device number 81h 80h Protection Register Lock 10
AI07563
Table 10.
Protection Register locks
Lock Description
Number
Address
Bits Bit 0 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Protects 64 bits of OTP area, address 85h to 88h in PR0
Lock 1
80h
Bit 1
Bits 2 to 15 Reserved Bit 0 Bit 1 Bit 2 ---Lock 2 89h Protects 128 bits of OTP area PR1 Protects 128 bits of OTP area PR2 Protects 128 bits of OTP area PR3 ---Protects 128 bits of OTP area PR14 Protects 128 bits of OTP area PR15 Protects 128 bits of OTP area PR16
Bit 13 Bit 14 Bit 15
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M58PR512LE, M58PR001LE
Program operations
5
Program operations
The M58PR512LE and M58PR001LE have innovative features specially developed to improve the storage flexibility and efficiency of NOR flash memory arrays. Data and code can be stored more efficiently by using the right combination of program methods and program modes. There are two types of program methods that use commands that consist of one or more sequential bus write operations interpreted by the command interface:

Single word program method, which uses the Program command. Buffered program method, which uses either the Buffer Program command or the Buffer Enhanced Factory Program command. Control program mode Object program mode.
There are two program modes:

The control program mode supports the two program methods, whereas the object program mode only supports the buffered program method. This new logical organization of program operations is made possible by the device architecture, and, in particular, by the new concept of program regions.
5.1
Program regions
Each flash memory block is divided into 256 program regions (see Figure 7: Program regions configured in control or object program mode). Erase operations have a block granularity, whereas program operations have a program region granularity. The user can configure each program region to be programmed either in the control program mode or in the object program mode. A given block can contain program regions configured in the control program mode and others configured in the object program mode. Special care should be taken when selecting the programming mode for the program regions because once the program regions are configured, their program mode cannot be changed until the entire block is erased. Each program region is split into 32 segments of 32 bytes and each segment is subdivided into two halves, 'A' and 'B'. Address bit A3 determines whether a bit belongs to the 'A' half (A3 = 0) or to the 'B' half (A3 = 1).
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Program operations
M58PR512LE, M58PR001LE
5.2
Program modes
There are two program modes, which allow the flash memory to store different types of data: control program mode and object program mode.
5.2.1
Control program mode
The control program mode is best suited to the storage of small, dynamic information. Typically such data is contained within one program region and it is frequently updated and/or new data is added to it. Program regions are configured in the control program mode by programming data only to the 'A' halves (bit A3= 0) of the segments they contain. The 'B' halves of the segments must remain erased, meaning that they should not contain any zeros (see Figure 7: Program regions configured in control or object program mode). In a program region of 1 Kbyte configured in the control program mode, only 512 bytes of data can be stored. When the program regions are configured in the control program mode, any program method can be used: the single word or the buffered program methods. Once a program region has been configured in the control program mode, if a zero is written to a 'B' half of one of its segments, the program operation is terminated and an error is generated. The status register bits SR4 and SR9 are set to `1'. (Refer to Status register and to Table 12: Relationships between program methods and program modes for details.) The program mode of a program region configured in the control program mode can only be changed by first erasing the block that contains the program region.
5.2.2
Object program mode
The object program mode is best suited to the storage of large amounts of static information. In a program region of 1 Kbyte configured in the object program mode, 1 Kbyte of data can be stored. When a program region is configured in the object program mode, it cannot be reprogrammed or have new data added without first erasing the entire block that contains the program region. Program regions are configured in the object program mode simply by programming at least one bit in the 'B' half (A3 = 1) of one of the segments they contain. If the programmed data is smaller than 1 Kbyte, the unused space remains in the erased state (all the bits set to FFFFh), but can no longer be used to program data. See Figure 7: Program regions configured in control or object program mode. When the program regions are configured in the object program mode, only the buffered program methods can be used. If an attempt is made to use the single word program method, the program operation is aborted and status register error bits SR4 and SR8 are set to `1'. (Refer to Status register and to Table 12: Relationships between program methods and program modes, for details.)
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M58PR512LE, M58PR001LE Figure 7.
Program operations
Program regions configured in control or object program mode
Program region in control program mode Data 1 Data 2 Data 4 FFFFFFFF FFFFFFFF SEGMENT 31 SEGMENT 30 SEGMENT 3 SEGMENT 2 SEGMENT 1 SEGMENT 0 Data 3
128 Kword BLOCK Program region 0 1 Kbyte (512 byte programmable) Program region 1 1 Kbyte (512 byte programmable)
...
Data (n - 4) Data (n - 3) Data (n - 1) Data n Data (n - 2) FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF B halves (A3 = 1)
: : : : :
A halves (A3 = 0)
Program region in object program mode FFFFFFFFFFFFFFFF Program region 254 1 Kbyte (512 byte programmable) Program region 255 1 Kbyte (512 byte programmable) FFFFFFFFFFFFFFFF SEGMENT 31 SEGMENT 30 SEGMENT 3 SEGMENT 2 Object SEGMENT 1 SEGMENT 0 1 Kbyte
ai10135
...
FFFFFF
5.3
Program methods
The device supports two types of program methods:

Single word program method, which is used to program a single word to a specific address of the memory array. Buffered program methods, which can be split into two different methods: - Buffer program method, which uses the device's write buffer to speed up programming. The data is written into the write buffer and then programmed to the specified block address. Buffer enhanced factory program method, which is developed to speed up programming in manufacturing environments where the programming time is critical. The data is written in the write buffer and then programmed to the specified block.
-
The following sections describe the relationship between program commands and program methods in detail. See Table 12: Relationships between program methods and program modes and Table 11: Program methods available with each program mode.
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Program operations
M58PR512LE, M58PR001LE
5.3.1
Single word program method
The single word program method is based on the Program command. It is only supported by program regions configured in the control program mode. If the single word program method is attempted in a program region configured in the object program mode, the program operation is aborted and status register bits SR4 and SR8 are set. See Section 4: Command interface for a detailed description of the Program command. In program regions configured in the control program mode, the Program command can be issued several times. Using the single word program method to program one or more bits to '0' in the 'B' halves of the segments (A3 = 1) of an erased or already programmed program region generates an error:

In the case of an erased program region, this is considered an illegal operation that sets status register bits SR4 and SR9. In the case of an already programmed program region, an error is always generated because: - - To be able to write to a program region configured in the object program mode, the entire block that contains the program region must be erased first. It is not allowed to write to the 'B' halves of the segments of a program region configured in the control program mode.
5.3.2
Buffer program method
The buffer program method is based on the Buffer Program command and uses a 1 Kbyte write buffer to speed up programming. The data is written to the write buffer and then programmed to the specified main array location. The buffer program method is supported regardless of the program mode of the program regions. When using the buffer program method in a program region configured in the object program mode, the start address must be aligned to the 1 Kbyte write buffer. When using the buffer program method in a program region configured in the control program mode, the address to be programmed must be located inside the 'A' halves of the program region's segments (addresses with A3 = 0) and the 'B' halves of the segments (addresses with A3= 1) must be filled only with FFFFh data. The Buffer Program command can be issued several times to program regions configured in the control program mode. The Buffer Program command can only be issued once in program regions configured in the object program mode. Attempts to program the same program regions by re-issuing the Buffer Program command leads to data corruption. See Section 4: Command interface for a detailed description of the Buffer Program command.
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M58PR512LE, M58PR001LE
Program operations
5.3.3
Buffer enhanced factory program method
The buffer enhanced factory program method is based on the Buffer Enhanced Factory Program command. The buffer enhanced factory program method is supported by the program regions, regardless of the program mode in which they are configured. In this program method, the program region (1 Kbyte) must be completely filled, regardless of the program mode used. If the size of the data to be written is less than 1 Kbyte, the remaining addresses in the program region must be filled with FFFFh. When using the buffer enhanced factory program method in a program region configured in the control program mode, the addresses to be programmed must be located in the 'A' half of the program regions' segments (A3 = 0) and the 'B' half of the segments (A3 = 1) must be filled only with FFFFh. See Section 4: Command interface for a detailed description of the Buffer Enhanced Factory Program command. Table 11. Program methods available with each program mode
Program methods(1) Program mode Buffered program Single word program X Buffer program X X Buffer enhanced factory Program X X
Control program mode Object program mode
1. X means available.
Table 12.
Relationships between program methods and program modes
Program method
Program region Address bit A3 status value
Buffered program Buffer program Buffer enhanced factory program Single word program
A3 = 0 ('A' half) Erased
Program region configured in control program mode
Program region configured in control program mode Not allowed. Program aborted, status register error bits SR4 and SR9 set
Program region configured in object A3 = 1 ('B' half) program mode A3 = 0 ('A' half) Program operation successful Control program mode Object program mode A3 = 1 ('B' half)
Not allowed. Program aborted, status register error bits SR4 and SR9 set
A3 = 0 ('A' half) Subsequent program not allowed. A3 = 1 ('B' half) Program aborted, status register error bits SR4 and SR8 set
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Status register
M58PR512LE, M58PR001LE
6
Status register
The status register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the status register (refer to Section 4.2 for more details on the command itself). To output the contents, the status register is latched and updated on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. The status register can only be read using single asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the status register during program and erase operations if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR9, SR8, SR5, SR4, SR3 and SR1 give information on errors. They are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the status register should be reset before issuing another command. The bits in the status register are summarized in Table 13: Status register bits. Refer to Table 13 in conjunction with the following text descriptions.
6.1
Control program mode status bit (SR9)
The control program mode status bit, SR9, indicates whether an error occurred while writing to a program region that is configured in control program mode. The SR9 bit should be read once the Program/Erase Controller status bit SR7 is set to `1' (Program/Erase Controller inactive). SR9 is set to 1 when the user attempts to program object data in a control mode region. When:

SR9 = 0, the program operation completed successfully. SR9 = 1, the program operation failed.
Once set to `1', SR9 can only be cleared by issuing a Clear Status Register command or through a hardware reset. SR9 should be cleared before a new program command is issued, otherwise the new command appears to fail.
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M58PR512LE, M58PR001LE
Status register
6.2
Object program mode status bit (SR8)
The object program mode status bit, SR8, indicates whether an error occurred while writing to a program region that was configured in the object program mode. The SR8 bit should be read once the Program/Erase Controller status bit SR7 is set to `1' (Program/Erase Controller inactive). SR8 is set to 1 when the user attempts to rewrite an object mode region. When:

SR8 = 0, the program operation completed successfully. SR8 = 1, the program operation failed.
Once set, SR8 can only be cleared by issuing a Clear Status Register command or through a hardware reset. SR8 should be cleared before a new program command is issued, otherwise the new command appears to fail.
6.3
Program/Erase Controller status bit (SR7)
The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When:

SR7 = 0, the Program/Erase Controller is active. SR7 = 1, the Program/Erase Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller status bit is set to '0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is set to '1'.
6.4
Erase suspend status bit (SR6)
The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When:

SR6 = 0, no Program/Erase Suspend command has been issued. SR6 = 1, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.
The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is set to '1' (Program/Erase Controller inactive). SR6 is set within the erase suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering suspend mode. When a Program/Erase Resume command is issued, the erase suspend status bit is reset to '0'.
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Status register
M58PR512LE, M58PR001LE
6.5
Erase status bit (SR5)
The erase status bit identifies if there is an error during a block erase operation. When:

SR5 = 0, no error occurred. SR5 = 1, the Program/Erase Controller applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly.
The erase status bit should be read once the Program/Erase Controller Status bit is set to '1' (Program/Erase Controller inactive). Once set, the erase status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new erase command is issued, otherwise the new command appears to fail.
6.6
Program status bit (SR4)
The program status bit identifies if there is an error during a program operation. The program status bit should be read once the Program/Erase Controller status bit is set to `1' (Program/Erase Controller inactive). When:

SR4 = 0, no error occurred. SR4 = 1, the Program/Erase Controller applied the maximum number of pulses to the word and still failed to verify that it programmed correctly.
Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the program status bit to '1'. If VPP is different from VPPH, SR4 remains set to '0' and the attempt is not shown. Once set to '1', the program status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program command is issued, otherwise the new command appears to fail.
6.7
VPP status bit (SR3)
The VPP status bit identifies an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation. When:

SR3 = 0, the voltage on the VPP pin is sampled at a valid voltage. SR3 = 1, the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the memory is protected, and program and erase operations cannot be performed.
Once set to `1', the VPP status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program or erase command is issued, otherwise the new command appears to fail.
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M58PR512LE, M58PR001LE
Status register
6.8
Program Suspend Status bit (SR2)
The program suspend status bit indicates that a program operation has been suspended in the addressed block. The program suspend status bit is onlyconsidered valid when the Program/Erase Controller status bit is set to `1' (Program/Erase Controller inactive). When:

SR2 = 0, no Program/Erase Suspend command has been issued. SR2 = 1, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command.
SR2 is set within the program suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering suspend mode. When a Program/Erase Resume command is issued, the program suspend status bit is reset to `0'.
6.9
Block protection status bit (SR1)
The block protection status bit dentifies if a program or block erase operation has tried to modify the contents of a locked block. When:

SR1 = 0, no program or erase operation has been attempted on a locked block. SR1 = 1, a program or erase operation has been attempted on a locked block.
Once set to `1', the block protection status bit must be cleared by a Clear Status Register command or a hardware reset. This must be done before a new program or erase command is issued, otherwise the new command appears to fail.
6.10
Bank write/multiple word program status bit (SR0)
The bank write status bit indicates if the addressed bank is programming or erasing. The bank write status bit is only considered valid when the Program/Erase Controller status bit SR7 is set to `0'. When:

SR0 = 0 and SR7 = 0, the addressed bank is executing a program or erase operation. SR0 = 1 and SR7 = 0, a program or erase operation is being executed in a bank other than the one being addressed.
During buffer enhanced factory program operations the multiple word program bit, SR0, shows if the device is ready to accept a new word to be programmed to the memory array. When:

SR0 = 0, the device is ready for the next word. SR0 = 1, the device is not ready for the next word.
For further details on how to use the status register, see the flowcharts and pseudocodes provided in Appendix C.
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Status register Table 13.
Bit
M58PR512LE, M58PR001LE Status register bits
Name Type Logic level(1) Definition
SR15Reserved(2) SR10 Control program mode status 1 Error 0 Object program mode status 1 Error 0 1 SR7 P/EC status Erase suspend status Erase status Status 0 1 Status 0 1 SR5 Error 0 1 SR4 Program status Error 0 1 SR3 VPP status Program suspend status Block protection status Error 0 1 Status 0 1 Error 0 No operation to protected blocks SR7 = `1' Not allowed 1 SR7 = `0' Bank write status Status SR7 = `1' 0 SR0 Multiple word program status (buffer enhanced factory program mode) SR7 = `0' Program or erase operation in addressed bank Program or erase operation in a bank other than the addressed bank No program or erase operation in the device Program in progress or completed Program/erase on protected block, abort Program success VPP invalid, abort VPP OK Program suspended Erase success Program error Erase in progress or completed Erase error SR6 Busy Erase suspended Program error in program region configured in control program mode Program successful Program error in program region configured in object program mode Program successful Ready
SR9
SR8
SR2
SR1
SR7 = `1' Not allowed 1 SR7 = `0' Status 0 SR7 = `0' The device is ready for the next word
1. Logic level '1' is High, '0' is Low. 2. Reserved bits should always be reset to `0'.
The device is not ready for the next word or is going to exit BEFP mode
SR7 = `1' The device is exiting from BEFP
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M58PR512LE, M58PR001LE
Configuration register
7
Configuration register
The configuration register configures the type of bus access that the memory performs. Refer to Section 10: Read modes for details on read operations. The configuration register is set through the command interface using the Set Configuration Register command. The configuration register is volatile: after a reset or a powerdown/power-up sequence, the register is set for asynchronous read (CR15=1) and all bits return to their default value. The configuration register bits are described in Table 15. They specify the selection of the burst length, burst X latency and the read operation. Refer to Figure 8 and Figure 9 for examples of synchronous burst configurations.
7.1
Read select bit (CR15)
The read select bit, CR15, switches between asynchronous and synchronous read operations. When:
CR15 = 0: - - Read operations in the main array are performed in synchronous burst mode, Operations to read the status register, electronic signature, CFI and EFA are performed in single synchronous mode (See Section 10.3: Single synchronous read mode for details). Read operations in the main array are performed in Asynchronous page mode, Operations to read the status register, electronic signature, CFI and EFA are performed in asynchronous random access mode.
CR15 = 1: - -
Synchronous burst read can be performed across banks. On reset or power-up the read select bit is set to '1' for asynchronous access.
7.2
X latency bits (CR14-CR11)
The X latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X latency bits can only assume the values in Table 15: Configuration register. Table 14 shows how to set the X latency parameter, taking into account the frequency used to read the flash memory in synchronous mode. Refer to Figure 8: X latency and data output configuration example for an example waveform.
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Configuration register Table 14. X latency settings
fmax 40 MHz 54 MHz 66 MHz 108 MHz tKmin 25 ns 19 ns 15 ns 9 ns
M58PR512LE, M58PR001LE
X latency 4 5 6 10
7.3
Wait polarity bit (CR10)
The wait polarity bit sets the polarity of the Wait signal used in synchronous burst read mode. When:

CR10 = 0, the Wait signal is active Low. CR10 = 1, the Wait signal is active High.
During synchronous burst read mode the Wait signal indicates whether the data output is valid or a Wait state must be inserted.
7.4
Wait configuration bit (CR8)
The wait configuration bit is used to control the timing of the Wait output pin, WAIT, in synchronous burst read mode. When:

CR8 = 0, the Wait output pin is asserted during the wait state. CR8 = 1, the Wait output pin is asserted one data cycle before the wait state.
When WAIT is asserted, data is not valid and when WAIT is de-asserted, data is valid.
7.5
Burst length bits (CR2-CR0)
The burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 8 words, 16 words, or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, the device asserts the Wait signal to indicate that a delay is necessary before the data is output. In continuous burst mode, if the starting address is not aligned to the 16-word boundary, Wait is asserted when the burst sequence crosses the first 16-word boundary. This indicates that the device needs an internal delay to read the successive words in the array.
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M58PR512LE, M58PR001LE
Configuration register
In the worst case scenario, the number of wait states is one clock cycle less than the latency setting. Wait is asserted only once during a continuous burst access. See also Table 16: Burst type definition. CR9, CR7, CR6, CR5, CR4 and CR3 are reserved for future use. Table 15.
Bit CR15
Configuration register
Description 0 Read Select 1 0011 0100 0101 0110 0111 1000 1001 Asynchronous read (default at power-on) 3 Clock latency 4 Clock latency 5 Clock latency 6 Clock latency 7 Clock latency 8 Clock latency 9 Clock latency 10 Clock latency 11 Clock latency 12 Clock latency 13 Clock latency 14 Clock latency 15 Clock latency (default) Value Synchronous read Description
CR14-CR11
X latency 1010 1011 1100 1101 1110 1111
Other configurations reserved 0 CR10 CR9 CR8 CR7-CR3 Wait polarity 1 Reserved(1) Wait configuration Reserved(1) 010 CR2-CR0 Burst length 011 111
1. Reserved bits should be cleared to `0'.
WAIT is active Low (default) WAIT is active High
0 1
WAIT is active during wait state WAIT is active one data cycle before wait state (default)1
8 words (wrap only) 16 words (wrap only) Continuous (default, no wrap only)
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Configuration register Table 16. Burst type definition
8 words 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 16 words
M58PR512LE, M58PR001LE
Start address 0 1 2 3 ... 7 ... 12 13 14 15
Continuous burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9...
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13...
12-13-14-15-8-9-10-11 13-14-15-8-9-10-11-12 14-15-8-9-10-11-12-13 15-8-9-10-11-12-13-14
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
12-13-14-15-16-17... 13-14-15-16-17-18... 14-15-16-17-18-19... 15-16-17-18-19-20...
Figure 8.
X latency and data output configuration example
X-latency 1st cycle 2nd cycle 3rd cycle 4th cycle
K
E
L
Amax-A0
VALID ADDRESS tQVK_CPU tKHQV tKHKH
DQ15-DQ0 VALID DATA VALID DATA
AI08904b
1. The settings shown are X latency = 4. tQVK_CPU is the data setup time required by the system CPU.
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M58PR512LE, M58PR001LE Figure 9.
E
Configuration register
Wait configuration example
K
L
Amax-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI12859
57/123
Enhanced configuration register
M58PR512LE, M58PR001LE
8
Enhanced configuration register
The ECR (enhanced configuration register) enables the deep power-down mode and configures the output driver strength. It is set through the command interface using the Set Enhanced Configuration Register command. The contents of the ECR can be read by issuing the Read Electronic Signature command, and then by reading from the bank base address + 06h. The ECR is volatile: after a reset or a power-down/power-up sequence the register is set to the default value. The configuration register bits are described in Table 17.
8.1
Deep power-down mode bit (ECR15)
The deep power-down mode bit, ECR15, enable the deep power-down mode. The device can only enter the deep power-down mode from standby, by, in any order, asserting the DPD pin and setting ECR15 to `1'. When the device is in the deep power-down mode, de-asserting the DPD pin and/or resetting ECR15 causes the device to revert to standby mode.
8.2
Deep power-down polarity bit (ECR14)
The deep power-down polarity bit sets the polarity of the DPD signal. When:

ECR14 = 0, the DPD signal is active Low (default). ECR14 = 1, the DPD signal is active High.
8.3
Output driver control bits (ECR2-ECR0)
The output driver control bits, ECR0, ECR1, and ECR2 select the output driver impedance best suited to the system requirements. After reset or power-up the output driver control bits are set to the enhanced configuration register default value (ECR2-ECR0 = 100, that is 30 (30 pF) (default)). Optimum performance is only achieved if the output driver impedance is properly configured. Once a configuration has been selected, all data and wait output drivers are set to the same setting. Table 17 lists the output driver impedances at VDDQ/2 and the loads that correspond for each ECR2-ECR0 bit configuration.
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M58PR512LE, M58PR001LE Table 17.
Bit ECR15
Enhanced configuration register
Enhanced configuration register
Description Deep power-down mode 1 0 DPD mode enabled DPD is active Low (default) DPD is active High Value 0 Description DPD mode disabled (default)
ECR14 ECR13-ECR3
DPD polarity 1 Reserved
(1)
001 010 011 ECR2-ECR0 Output driver Impedance 100 101 110
90 (10 pF) 60 (15 pF) 45 (20 pF) 30 (30 pF) (default) 20 (35 pF) 15 (40 pF)
Other configurations reserved
1. Reserved bits should be cleared to `0'.
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Extended flash array (EFA)
M58PR512LE, M58PR001LE
9
Extended flash array (EFA)
In addition to its main array, the M58PRxxxLE features an EFA that is divided into 4 blocks of 4 KWords each. See Table 4: EFA memory map. The EFA blocks are accessed through a separate set of commands (see Section 4: Command interface for details). The operations available on the EFA blocks are asynchronous random access read, single synchronous read, (single word) program, erase, block lock, block unlock, and block lockdown. The EFA blocks support program/erase suspend and dual operations with the main array. Dual operations between the EFA and the OTP area are not supported. See Table 20: Dual operation limitations for details.
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M58PR512LE, M58PR001LE
Read modes
10
Read modes
Read operations can be performed in two different ways depending on the settings in the configuration register. If the clock signal is `don't care' for the data output, the read operation is asynchronous. If the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the configuration register. (See Section 7: Configuration register for details). All banks support both asynchronous and synchronous read operations.
10.1
Asynchronous read mode
In asynchronous read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, such as the memory array, status register, common flash interface or electronic signature, depending on the command issued. CR15 in the configuration register must be set to `1' for asynchronous operations. Asynchronous read operations can be performed in two different ways, asynchronous random access read and asynchronous page read. Only asynchronous page read takes full advantage of the internal page storage, therefore, different timings are applied. In asynchronous read mode a page of data is internally read and stored in a page buffer. The page has a size of 16 words and is addressed by address inputs A0, A1, A2 and A3. During the page access, Amax-A4 and L must remain stable. The first read operation within the page has a longer access time (tAVQV, Random access time); subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes then the normal, longer timings apply again. Read operations to read non-array data (status register, electronic signature, CFI) should be performed in asynchronous single word mode. If the asynchronous page mode is used to read non-array data, only the first output data is valid and all subsequent data is not accurately determined. The asynchronous page read mode is not available in the EFA. The device features an automatic standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. In this state the power consumption is reduced to the standby value and the outputs are still driven. In asynchronous read mode, the Wait signal is always de-asserted. See Table 28: Asynchronous read AC characteristics, Figure 12: Asynchronous random access read AC waveforms and Figure 13: Asynchronous page read AC waveforms for details.
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Read modes
M58PR512LE, M58PR001LE
10.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read status register, read CFI, read electronic signature and read EFA, single synchronous read or asynchronous random access read must be used. In synchronous burst read mode, the flow of the data output depends on parameters that are configured in the configuration register. A burst sequence starts at the first clock edge after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR14-CR11 of the configuration register. The number of words to be output during a synchronous burst read operation can be configured as 8 words, 16 words, or continuous (burst length bits CR2-CR0). The Wait signal may be asserted to indicate to the system that an output delay will occur. This delay depends on the starting address of the burst sequence and on the burst configuration. Wait is asserted during the X latency, the wait state, and at the end of an 8- and 16-word burst. It is only de-asserted when output data is valid. In continuous burst read mode, a wait state occurs when crossing the first 16-word boundary if the start address is not 16-word aligned. The Wait signal can be configured to be active Low or active High by setting CR10 in the configuration register. See Table 29: Synchronous read AC characteristics and Figure 14: Synchronous burst read AC waveforms for details.
10.3
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data until the burst length requirements are satisfied (according to configuration register bits CR2-CR0). Single synchronous read operations are used to read the EFA, electronic signature, status register, CFI, block protection status, configuration register status or Protection Register. When the addressed bank is in read CFI, read status register or read electronic signature mode, the Wait signal is asserted during the X latency, the wait state and at the end of a 4-, 8- and 16-word burst. It is only de-asserted when the output data is valid. See Table 29: Synchronous read AC characteristics and Figure 14: Synchronous burst read AC waveforms for details.
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M58PR512LE, M58PR001LE
Dual operations and multiple bank architecture
11
Dual operations and multiple bank architecture
The multiple bank architecture of the M58PRxxxLE gives greater flexibility for software developers to split the code and data spaces within the memory array. The dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also, if the suspended operation was erase then a program command can be issued to another block. This means the device can have one block in erase suspend mode, one programming and other banks in read mode. Bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58PRxxxLE device. Dual operations between the EFA and either of the CFI, the OTP, or the electronic signature memory space are not allowed. Table 20 shows which dual operations are allowed or not between the CFI, the OTP, the electronic signature locations and the memory array. Table 18 and Table 19 show the dual operations possible in other banks and in the same bank. Table 18. Dual operations allowed in other banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Program, Program/ Program/ Read Block Status CFI Electronic Buffer Erase Erase EFA Erase Register Query Signature Program Suspend Resume Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes Yes - - - - Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program suspended Erase suspended
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Dual operations and multiple bank architecture Table 19.
Status of bank
M58PR512LE, M58PR001LE
Dual operations allowed in same bank
Commands allowed in same bank Read Array Yes -
(1) (1)
Read Status Register Yes Yes Yes Yes Yes
Read Read Program, Program/ Program/ Read Block CFI Electronic Buffer Erase Erase EFA Erase Query Signature Program Suspend Resume Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes(2) Yes - - - - Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program suspended Erase suspended
-
Yes(2) Yes(2)
1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has completed. 2. Not allowed in the block that is being erased or in the program region that is being programmed.
Table 20.
Dual operation limitations
Main array bank Program/erase Comments While programming or erasing in a main array bank, the OTP, CFI data and EFA blocks may be read from any other bank. While programming to the OTP area, read operations are only allowed in the other main array banks. Access to EFA data or CFI data is not allowed. While programming or erasing an EFA block, it is not allowed to read OTP or CFI data. Read operations to the banks whose addresses are not being used to address the EFA, are supported.
OTP, EFA or CFI data Read
Program
Read
Program/erase
Read
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M58PR512LE, M58PR001LE
Block locking
12
Block locking
The M58PRxxxLE features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.

Lock/unlock - this first level allows software only control of block locking. Lock-down - this second level requires hardware interaction before locking can be changed. VPP VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to locked, unlocked, and locked-down. Table 21 defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 29 shows a flowchart for the locking operations.
12.1
Reading a block's lock status
The lock status of every block can be read in the read electronic signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 9 output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering lock-down. DQ1 indicates the lock-down status and is set by the lockdown command. DQ1 cannot be cleared by software, only by a hardware reset or powerdown. The following sections explain the operation of the locking system.
12.2
Locked state
The default status of all blocks on power-up or after a hardware reset is locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block returns an error in the status register. The status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. An unlocked block can be locked by issuing the Lock command.
12.3
Unlocked state
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)) can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by issuing the unlock command.
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Block locking
M58PR512LE, M58PR001LE
12.4
Lock-down state
Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the Lock-down command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The lock-down function is dependent on the Write Protect, WP, input pin. When WP = 0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP = 1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the lock-down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP = 0 blocks that were previously locked-down return to the Lock-down state (0,1,x) regardless of any changes that were made while WP = 1. Device reset or power-down resets all blocks, including those in lock-down, to the locked state.
12.5
Locking operations during erase suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next, write the desired lock command sequence to a block and the lock status is changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an Erase Suspend of the same block, the locking status bits are changed immediately, but when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend.
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M58PR512LE, M58PR001LE Table 21. Lock status
Next protection status(1) (WP, DQ1, DQ0) After Block Lock command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 After Block Unlock command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-down command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1
Block locking
Current protection status(1) (WP, DQ1, DQ0) Current state 1,0,0 1,0,1
(2)
Program/erase allowed yes no yes no yes no no
After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0(3)
1,1,0 1,1,1 0,0,0 0,0,1
(2)
0,1,1
1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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Program and erase times and endurance cycles
M58PR512LE, M58PR001LE
13
Program and erase times and endurance cycles
The program and erase times and the number of program/ erase cycles per block are shown in Table 22. Exact erase times may change depending on the memory array condition. The best scenario is when all the bits in the block are at `0' (pre-programmed). The worst scenario is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the Erase time. In the M58PRxxxLE the maximum number of program/erase cycles depends on the VPP voltage supply used. Table 22. Program/erase times and endurance cycles(1) (2)
Parameter EFA block (4 KWord) Erase Main array block 128 KWord) Single cell(4) Word Program(5) 0.9 50 250 50 250 2.15 0.2 0.55 20 20 100 000 cycles 100 000 3.2 ms 4 230 500 230 500 4.3 0.94 1.1 30 30 s s s s s ms s s s s Condition Min Typ 0.7 Typical after 100 kW/E Max cycles 2.5 Unit s
Buffer Program Single word(4) Program(3) VPP = VDD Word Program(5)
Buffer Program Buffer (512 words) (Buffer Program) EFA block (4 KWord) Main array block (128 KWord) (Buffer Program) Program Suspend Latency Erase Main array block Program/Erase cycles (per block) EFA block Blank Check Main array block
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M58PR512LE, M58PR001LE Table 22.
Program and erase times and endurance cycles
Program/erase times and endurance cycles(1) (2) (continued)
Parameter EFA block (4 KWord) Condition Min Typ 0.7 0.9
(5)
Typical after 100 kW/E Max cycles 2.5 4 230 230
Unit s s s s s
Erase Main array block (128 KWord) Single cell
(4)
Word Program
50 50 4.2 2.15 2.15 0.55 0.55 0.2 100 000
Word Program(5) Single word(4) Buffer Enhanced Factory Program(4) Buffer Program Buffer (512 words) Buffer Enhanced Factory Program Buffer Program Main block (128 KWords) Buffer Enhanced Factory Program
VPP = VPPH
Program(3)
4.3
ms ms
1.1
s s
EFA block (4 KWords) Main array block (128 KWords) Program/Erase cycles (per block) EFA block (4 KWords) Blank Check Main array block
0.94
s cycles
100 000 3.2 ms
1. TA = -30 to 85 C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V. 2. Values are liable to change with the external system-level overhead (command sequence and status register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device. 5. The first Word Program in a program region will take 115 s, the subsequent words will take 50 s to program.
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Maximum ratings
M58PR512LE, M58PR001LE
14
Maximum ratings
Stressing the device above the ratings listed in Table 23: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality documents. Table 23.
Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH
Absolute maximum ratings
Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage Supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH -30 -30 -65 -1 -1 -1 -1 Max 85 85 125 3 3 3 10 100 100 C C C V V V V mA hours Unit
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M58PR512LE, M58PR001LE
DC and AC parameters
15
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables in this section are derived from tests performed under the measurement conditions summarized in Table 24: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 24. Operating and AC measurement conditions
Parameter VDD supply voltage VDDQ supply voltage VPP supply voltage (factory environment) VPP supply voltage (application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQ VDDQ/2 Min 1.7 1.7 8.5 0.9 -30 30 3 Max 2.0 2.0 9.5 2.0 85 Units V V V V C pF ns V V
Figure 10. AC measurement I/O waveform
VDDQ VDDQ/2 0V
AI06161
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DC and AC parameters Figure 11. AC measurement load circuit
VDDQ
M58PR512LE, M58PR001LE
VDDQ VDD 16.7 k DEVICE UNDER TEST 0.1 F 0.1 F CL 16.7 k
CL includes JIG capacitance
AI06162
Table 25.
Symbol CIN COUT
Capacitance(1)
Parameter Input capacitance Output capacitance Test condition VIN = 0 V VOUT = 0 V Min 2 4 Max 8 8 Unit pF pF
1. Sampled only, not 100% tested.
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M58PR512LE, M58PR001LE Table 26.
Symbol ILI ILO
DC and AC parameters
DC characteristics - currents
Parameter Input leakage current Output leakage current Supply current Asynchronous read (f=5 MHz) Supply current Page read (f=13 MHz) 8 word Supply current Synchronous read (f=66 MHz) Test condition(1) 0 V VIN VDDQ 0 V VOUT VDDQ E = VIL, G = VIH 25 5 22 19 25 26 23 30 50 70 50 70 50 70 2 VPP = VPPH, VPP = VDD VPP = VPPH, VPP = VDD VPP = VPPH, VPP = VDD Program/erase in one bank, asynchronous read in another bank 35 35 35 60 Typ Max 1 1 30 10 27 21 29 31 25 37 160 A 1 Gbit 255 160 A 255 160 A 1 Gbit 255 45 50 55 50 85 A mA mA mA mA Unit A A mA mA mA mA mA mA mA mA
IDD1
16 word Continuous 8 word
Supply current Synchronous read (f = 108 MHz)
16 word Continuous 512 Mbit
IDD2
Supply current (reset)
RP = VSS 0.2 V
IDD3 IDD4(1) IDD5(2)
Supply current (standby) Supply current (automatic standby) Supply current (deep powerdown) Supply current (program)
E = VDDQ 0.2 V 512 Mbit K = VSS 1 Gbit E = VIL, G = VIH, RP = VIH 512 Mbit
IDD6 (3)
Supply current (erase) Supply current (blank check)
IDD7(3)(4)
Supply current (dual operations)
Program/erase in one bank, synchronous read (continuous, f = 108 MHz) in another bank E = VDDQ 0.2 V 512 Mbit K = VSS 1 Gbit VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD
65
92
mA
IDD8(3)
Supply current program/ erase suspended (standby) VPP supply current (program)
50 70 8 0.05 8 0.05 2
160 A 255 22 0.1 22 0.1 15 mA mA mA mA A
IPP1(3) VPP supply current (erase) IPP2 VPP supply current (read)
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DC and AC parameters Table 26.
Symbol IPP3(3) IPP4
M58PR512LE, M58PR001LE DC characteristics - currents (continued)
Parameter Test condition(1) VPP VDD VPP = VPPH VPP = VPP1 Typ 0.2 0.05 0.05 Max 5 0.1 0.1 Unit A mA mA
VPP supply current (standby, program/erase suspend) VPP supply current (blank check)
1. All inputs stable. 2. The DPD current is measured 40 s after entering the deep power-down mode. 3. Sampled only, not 100% tested. 4. VDD dual operation current is the sum of read and program or erase currents.
Table 27.
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH VLKOQ
DC characteristics - voltages
Parameter Input low voltage Input high voltage Output low voltage Output high voltage VPP program voltage-logic VPP program voltage factory Program or erase lockout VDD lock voltage RP pin extended high voltage VDDQ lock voltage 0.9 1 3.3 IOL = 100 A IOH = -100 A Program, erase Program, erase VDDQ -0.1 1.1 8.5 1.8 9.0 3.3 9.5 0.4 Test condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V V
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tAVAV VALID VALID tLHAX tAVQV tAXQX tAVLH
M58PR512LE, M58PR001LE
A0-Amax(1)
L(2) tLLLH tLLQV tELLH
E tELQV tELQX tEHQZ tEHQX
G tGLQV tGLQX Hi-Z tGLTV tELTV Hi-Z tGHTZ VALID tEHTZ tGHQX tGHQZ
Figure 12. Asynchronous random access read AC waveforms
DQ0-DQ15
WAIT(3)
Notes:
DC and AC parameters
1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE. 2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported. 3. WAIT is active Low.
AI12860b
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VALID ADDRESS tAVAV VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. VALID ADD. tLHAX tLLLH tLLQV tELQV tELQX
DC and AC parameters
A4-Amax(1)
A0-A3
VALID ADDRESS
tAVLH
L
tELLH
E
G tGLTV tELTV
Figure 13. Asynchronous page read AC waveforms
WAIT(2) tGLQV tGLQX VALID DATA Outputs Enabled VALID DATA tAVQV1
Hi-Z
DQ0-DQ15
VALID DATA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
VALID DATA
Valid Address Latch
Valid Data
Standby
M58PR512LE, M58PR001LE
Notes: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE. 2. WAIT is active Low.
AI12861c
M58PR512LE, M58PR001LE Table 28.
Symbol tAVAV tAVQV tAVQV1 tAXQX(1) tELTV tELQV(2) Read timings tELQX(1) tEHTZ tEHQX(1) tEHQZ
(1)
DC and AC parameters
Asynchronous read AC characteristics
Alt tRC tACC tPAGE tOH Parameter Address Valid to Next Address Valid Address Valid to Output Valid (random) Address Valid to Output Valid (page) Address Transition to Output transition Chip Enable Low to Wait Valid tCE tLZ Chip Enable Low to Output Valid Chip Enable Low to Output transition Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ Chip Enable High to Output transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output transition Output Enable Low to Wait Valid tOH tDF Output Enable High to Output transition Output Enable High to Output Hi-Z Output Enable High to Wait Hi-Z tAVADVH tELADVH tADVHAX Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address transition Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Max Min Min Min Min Max 108 MHz 66 MHz Unit 96 96 20 0 14 96 0 9 0 9 20 0 7 0 9 9 5 9 5 7 96 96 96 25 0 14 96 0 14 0 14 20 0 11 0 14 17 5 10 5 7 96 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tGLQV(2) tGLQX(1) tGLTV tGHQX(1) tGHQZ
(1)
tGHTZ tAVLH Latch timings tELLH tLHAX tLLLH tLLQV
tADVLADVH Latch Enable Pulse width tADVLQV Latch Enable Low to Output Valid (random)
1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV.
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VALID tKHQV tKHQX VALID VALID NOT VALID VALID tLLLH tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ
DC and AC parameters
DQ0-DQ15
Hi-Z
A0-Amax(4)
VALID ADDRESS
tAVLH
L
tLLKH
tAVKH
K(3)
tELKH
E tGHQX tGLQX tGHQZ
Figure 14. Synchronous burst read AC waveforms
G tGLTV tKHTV Note 2 tKHTX Note 2 Note 2 Valid Valid Data Flow Boundary Crossing Data tEHTZ
Hi-Z
WAIT X Latency
Address Latch
Standby
M58PR512LE, M58PR001LE
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.
AI12862b
M58PR512LE, M58PR001LE Figure 15. Single synchronous read AC waveforms
A0-Amax(1) VALID ADDRESS tAVKH L tLLKH K(2) tELKH tELQV E tGLQV tGLQX G tELQX DQ0-DQ15 Hi-Z tKHQV
DC and AC parameters
tGHTZ VALID tKHTV tGLTV
WAIT(2,3)
Hi-Z tLLTV
Notes: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge.
AI12863c
Figure 16. Clock input AC waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
79/123
DC and AC parameters Table 29.
Symbol tAVKH tELKH Synchronous Read timings tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH tLLTV Clock specifications tKHKH tKHKL tKLKH tf tr tCLK tCLKHAX tCLKHQV tCLKHQX tADVLCLK
H
M58PR512LE, M58PR001LE Synchronous read AC characteristics
Alt tAVCLKH tELCLKH Parameter Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Pulse width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Clock High to Address transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output transition Clock High to WAIT transition Latch Enable Low to Clock High Latch Enable Low to WAIT Valid Clock period (f=66 MHz) Clock period (f=108 MHz) Clock High to Clock Low Clock Low to Clock High Clock fall or rise time Max 2 3 ns Min Min Min Max Min Max Min Min Max Min Min Min Min 9 2.5 0.3 3.5 108 MHz 5 5 9 9 5 7 2 5 14 66 MHz 5 5 11 11 5 11 3 5 14 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Sampled only, not 100% tested. 2. For other timings please refer to Table 28: Asynchronous read AC characteristics.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAV tWHAX VALID ADDRESS tLHAX tLLLH
A0-Amax(1)
tAVLH
L tWHLL
tELLH
M58PR512LE, M58PR001LE
E tWHEH
tELWL
G tWHWL tWHGL
tGHWL
W tWLWH tWHEL tWHDX COMMAND CMD or DATA tWHWPL tWPHWH tQVWPL tWHQV STATUS REGISTER tELQV
tDVWH
Figure 17. Write AC waveforms, write enable controlled
DQ0-DQ15
WP tWHVPL tVPHWH tQVVPL
VPP tELKH
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
SET-UP COMMAND
Note: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE AI12864b
DC and AC parameters
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DC and AC parameters Table 30.
Symbol tAVAV tAVLH tAVWH(2) tDVWH tELLH tELWL Write Enable Controlled timings tELQV tELKH tGHWL tLHAX tLLLH tWHAV(2) tWHAX
(2)
M58PR512LE, M58PR001LE Write AC characteristics, write enable controlled(1)
Alt tWC Parameter Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High tDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High tCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock High Output Enable High to Write Enable Low Latch Enable High to Address transition Latch Enable Pulse width Write Enable High to Address Valid tAH tDH tCH Write Enable High to Address transition Write Enable High to Input transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low tWPH Write Enable High to Write Enable Low Write Enable High to Output Valid tWP Write Enable Low to Write Enable High Output (status register) Valid to VPP Low Output (status register) Valid to Write Protect Low tVPS VPP High to Write Enable High Write Enable High to VPP Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 108 MHz 66 MHz 96 5 40 40 9 0 96 5 14 5 7 0 0 0 0 20 0 20 20 116 40 0 0 200 200 200 200 96 5 40 40 10 0 96 5 17 5 7 0 0 0 0 20 0 20 20 116 40 0 0 200 200 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWHDX tWHEH tWHEL(3) tWHGL tWHLL(3) tWHWL tWHQV tWLWH tQVVPL
Protection timings 82/123
tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH
1. Sampled only, not 100% tested. 2. Meaningful only if L is always kept Low. 3. tWHELand tWHLL have this value when reading in the targeted bank or when reading after a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the configuration register have been issued, tWHEL is 0 ns.
PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVEH tEHAX VALID ADDRESS tLHAX tLLLH
A0-Amax(1)
tAVLH
L tELLH tEHWH
M58PR512LE, M58PR001LE
W tWLEL
G tGHEL tEHEL tEHGL
E tELEH tEHDX COMMAND CMD or DATA tEHWPL tWPHEH tQVWPL tWHEL tWHQV tELQV
tDVEH
Figure 18. Write AC waveforms, Chip Enable controlled
DQ0-DQ15
STATUS REGISTER
WP tEHVPL tVPHEH tQVVPL
VPP tELKH
K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI12865b
SET-UP COMMAND
DC and AC parameters
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Note: 1. Amax is equal to A24 in the M58PR512LE and to A25 in the M58PR001LE.
DC and AC parameters Table 31.
Symbol tAVAV tAVEH tAVLH tDVEH tEHAX tEHDX Chip Enable Controlled timings tEHEL tEHGL tEHWH tELKH tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL
(2)
M58PR512LE, M58PR001LE Write AC characteristics, Chip Enable controlled(1)
Alt tWC tWC Parameter Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High tDS tAH tDH Data Valid to Chip Enable High Chip Enable High to Address transition Chip Enable High to Input transition Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 108 MHz 66 MHz 96 40 5 40 0 0 20 0 0 5 40 9 96 14 5 7 20 116 0 200 200 0 0 200 200 96 45 5 40 0 0 20 0 0 5 45 10 96 17 5 7 20 116 0 200 200 0 0 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCPH Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low tCH Chip Enable High to Write Enable High Chip Enable Low to Clock High tCP Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address transition Latch Enable Pulse width Write Enable High to Chip Enable Low Write Enable High to Output Valid tCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Chip Enable High to Write Protect Low Output (status register) Valid to VPP Low Output (status register) Valid to Write Protect Low tVPS VPP High to Chip Enable High Write Protect High to Chip Enable High
tWHQV tWLEL tEHVPL Protection timings 84/123 tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH
1. Sampled only, not 100% tested. 2. tWHEL has this value when reading in the targeted bank or when reading after a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the configuration register have been issued, tWHEL is 0 ns.
M58PR512LE, M58PR001LE Figure 19. Reset and power-up AC waveforms
DC and AC parameters
W, E, G, L
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06976
tPLPH
Table 32.
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3)
Reset and power-up AC characteristics
Parameter Reset Low to Write Enable Low, Reset Low to Chip Enable Low, Reset Low to Output Enable Low, Reset Low to Latch Enable Low Reset High to Write Enable Low Reset High to Chip Enable Low Reset High to Output Enable Low Reset High to Latch Enable Low RP Pulse width Supply voltages High to Reset High Test condition During program During erase Other conditions Min Min Min 108 MHz / 66 MHz 25 30 80 Unit s s ns
Min
30
ns
Min Min
50 300
ns s
1. The device reset is possible but not guaranteed if tPLPH < 50 ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP to allow proper CPU initialization during power-up or reset.
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DC and AC parameters Figure 20. Deep power-down AC waveforms
tDPLDPH DPD E tEHDPL tDPHEL
M58PR512LE, M58PR001LE
Ai11625
Figure 21. Reset during deep power-down AC waveforms
DPD E tEHDPL RP tPHEL
Ai11626
Table 33.
Symbol tDPLDPH tEHDPL tDPHEL tPHEL
Deep power-down AC characteristics
Parameter Deep power-down asserted to Deep power-down de-asserted Chip Enable Low to deep powerdown asserted Deep power-down de-asserted to Chip Enable Low Reset High to Chip Enable Low During deep power-down Test condition Min Min Min Min 108 MHz/66 MHz 50 0 75 75 Unit ns s s s
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M58PR512LE, M58PR001LE
Package mechanical
16
Package mechanical
To meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a lead-free, second-level interconnect. In compliance with JEDEC Standard JESD97, the category of second-level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK specifications are available at: www.numonyx.com. Figure 22. TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline
D D1 FD
e
E
E1
SE
ddd
BALL "A1"
FE A e b A1 A2
BGA-Z79
1. Drawing is not to scale.
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Package mechanical Table 34.
M58PR512LE, M58PR001LE TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, mechanical data
Millimeters Inches Max 1.20 0.20 0.80 0.35 9.00 6.40 0.10 11.00 8.80 0.80 1.30 1.10 0.40 - - 10.90 11.10 0.433 0.346 0.031 0.051 0.043 0.016 - - 0.429 0.30 8.90 0.40 9.10 0.031 0.014 0.354 0.252 0.004 0.437 0.012 0.350 0.016 0.358 0.008 Typ Min Max 0.047
Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SE Min
Figure 23. TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline
D D1 FD
e
E E1
BALL "B1"
SE
ddd
FE A e b A1 A2
BGA-Z85
1. Drawing is not to scale.
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M58PR512LE, M58PR001LE Table 35.
Package mechanical
Stacked TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package mechanical data
millimeters inches Max 1.20 0.20 0.85 0.35 8.00 6.40 0.10 11.00 8.80 0.80 0.80 1.10 0.40 10.90 11.10 0.433 0.346 0.031 0.031 0.043 0.016 0.429 0.30 7.90 0.40 8.10 0.033 0.014 0.315 0.252 0.004 0.437 0.012 0.311 0.016 0.319 0.008 Typ Min Max 0.047
Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SE Min
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Part numbering
M58PR512LE, M58PR001LE
17
Part numbering
Table 36.
Example: Device type M58 Architecture P = multilevel, multiple bank, large buffer Operating voltage R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V Density 512 = 512 Mbit 001 = 1 Gbit Technology L = 65 nm technology multilevel design Memory organization E = uniform blocks Speed 96 = 96 ns Package ZAD = stacked TFBGA105 D stacked footprint. ZAC= stacked TFBGA107 C stacked footprint. Temperature range 5 = -30 to 85 C
Ordering information scheme
M58PR512L E 96 ZAD 5
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you.
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M58PR512LE, M58PR001LE
Block address tables
Appendix A
Block address tables
The following set of equations can be used to calculate a complete set of block addresses using the information contained in tables 37, 38, 39 and 40. To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: For the M58PR512LE: Bank_Number = Block_Number / 32 Block_Number_Offset = Block_Number - (Bank_Number x 32) For the M58PR001LE: Bank_Number = Block_Number / 64 Block_Number_Offset = Block_Number - (Bank_Number x 64) The Block Base Address is calculated using the formula below: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the Bank number and the Block Number from the Block Base Address: The Block Number, Bank Number and Block Number Offset can be calculated using the formulas below: For the M58PR512LE: Block_Number = address / 232 Bank_Number = Block_Number / 32 Block_Number_Offset = Block_Number -(Bank_Number x 32) For the M58PR001LE: Block_Number = address / 264 Bank_Number = Block_Number / 64 Block_Number_Offset = Block_Number - (Bank_Number x 64) Table 37. M58PR512LE - bank base addresses
Block numbers 0 - 31 32 - 63 64 - 95 96 - 127 128 - 159 160 - 191 192 - 223 224 - 255 Bank base address 0000000 0400000 0800000 0C00000 1000000 1400000 1800000 1C00000
Bank number 0 1 2 3 4 5 6 7
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Block address tables Table 38. M58PR001LE - bank base addresses
Block numbers 0 - 63 64 - 127 128 - 191 192 - 255 256 - 319 320 - 383 384 - 447 448 - 511
M58PR512LE, M58PR001LE
Bank number 0 1 2 3 4 5 6 7
Bank base address 0 800000 1000000 1800000 2000000 2800000 3000000 3800000
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M58PR512LE, M58PR001LE Table 39. M58PR512LE - block addresses
Block number offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Block address tables
Block base address offset 0000000 0020000 0040000 0060000 0080000 00A0000 00C0000 00E0000 0100000 0120000 0140000 0160000 0180000 01A0000 01C0000 01E0000 0200000 0220000 0240000 0260000 0280000 02A0000 02C0000 02E0000 0300000 0320000 0340000 0360000 0380000 03A0000 03C0000 03E0000
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Block address tables Table 40. M58PR001LE - block addresses
Block number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
M58PR512LE, M58PR001LE
Block base address offset 0000000 0020000 0040000 0060000 0080000 00A0000 00C0000 00E0000 0100000 0120000 0140000 0160000 0180000 01A0000 01C0000 01E0000 0200000 0220000 0240000 0260000 0280000 02A0000 02C0000 02E0000 0300000 0320000 0340000 0360000 0380000 03A0000 03C0000 03E0000 0400000 0420000 0440000
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M58PR512LE, M58PR001LE Table 40. M58PR001LE - block addresses (continued)
Block number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Block address tables
Block base address offset 0460000 0480000 04A0000 04C0000 04E0000 0500000 0520000 0540000 0560000 0580000 05A0000 05C0000 05E0000 0600000 0620000 0640000 0660000 0680000 06A0000 06C0000 06E0000 0700000 0720000 0740000 0760000 0780000 07A0000 07C0000 07E0000
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Common flash interface
M58PR512LE, M58PR001LE
Appendix B
Common flash interface
The common flash interface is a JEDEC approved, standardized data structure that can be read from the flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued the device enters CFI query mode and the data structure is read from the memory. Tables 41, 42, 43, 44, 45, 46, 47, 48, 49, 50 and 51 show the addresses used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ0-DQ7), and the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64-bit unique security number is written (see Figure 6: Protection Register memory map). This area can only be accessed in read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to read mode. Table 41.
Offset 000h 010h 01Bh 027h P A Reserved CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Alternate algorithm-specific extended query table Security code area
Query structure overview(1)
Sub-section name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing and voltage information Flash device layout Additional information specific to the primary algorithm (optional) Additional information specific to the alternate algorithm (optional) Lock Protection Register Unique device number and user programmable OTP
080h
1. The flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in tables 42, 43, 44 and 45. Query data is always presented on the lowest order data outputs.
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M58PR512LE, M58PR001LE Table 42.
Offset 000h 001h 002h00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah
Common flash interface
CFI query identification string
Sub-section name 0020h 8819h 880Fh Reserved 0051h 0052h 0059h 0000h 0002h offset = P = 000Ah 0001h 0000h 0000h value = A = 0000h 0000h Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm Address for primary algorithm extended query table (see Table 45) Alternate vendor command set and control interface ID code second vendor - specified algorithm supported Address for alternate algorithm extended query table P = 10Ah Query unique ASCII string "QRY" Manufacturer code Device code Reserved "Q" "R" "Y" M58PR512LE M58PR001LE Description Value ST 512 Mbits 1 Gbit
NA
NA
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Common flash interface Table 43.
Offset
M58PR512LE, M58PR001LE
CFI query system interface information
Data Description VDD logic supply minimum program/erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD logic supply maximum program/erase or write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply minimum program/erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply maximum program/erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical timeout per single byte/word program = 2n s Typical timeout for buffer program = 2 s Typical timeout per individual block erase = Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2 times typical Maximum timeout for buffer program = 2n times typical
n n n
Value
01Bh
0017h
1.7 V
01Ch
0020h
2V
01Dh
0085h
8.5 V
01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h
0095h 0006h 000Bh 000Ah 0000h 0002h 0002h 0002h 0000h
9.5 V 64 s 2048 s
2n
ms
1s NA 256 s 8192 s 4s NA
Maximum timeout per individual block erase = 2 times typical Maximum timeout for chip erase = 2n times typical
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M58PR512LE, M58PR001LE Table 44.
Offset 027h 001Bh 028h 029h 02Ah 02Bh 02Ch 0001h 0000h 000Ah 0000h 0001h 00FFh 0000h 01FFh 0000h 0000h 0004h
Common flash interface
Device geometry definition
Data 001Ah Description M58PR512LE device size = 2n in number of bytes M58PR001LE device size = 2 in number of bytes Flash device interface code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase block regions M58PR512LE erase block region 1 information Number of identical-size erase blocks = 00FFh+1 M58PR001LE erase block region 1 information Number of identical-size erase blocks = 01FFh+1 Erase block region 1 information Block size in region 1 = 0400h * 256 byte
n
Value 64 Mbytes 128 Mbytes x16 Async. 1024 bytes 1 255 511 256 Kbyte NA
02Dh 02Eh
02Fh 030h 031h 038h
Reserved Reserved for future erase block region information
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Common flash interface Table 45.
Offset (P)h = 10Ah
M58PR512LE, M58PR001LE
Primary algorithm-specific extended query table
Data 0050h 0052h Primary algorithm extended query table unique ASCII string "PRI" 0049h Description Value "P" "R" "I" "1" "4"
(P+3)h =10Dh 0031h Major version number, ASCII (P+4)h = 10Eh 0034h Minor version number, ASCII (P+5)h = 10Fh 00E6h Extended query table contents for primary algorithm. Address (P+5)h contains less significant byte (1 = Yes, 0 = No) (P+6)h = 110h 0007h (P+7)h = 111h 0000h bit 0 Chip Erase supported bit 1 Erase Suspend supported bit 2 Program Suspend supported bit 3 Legacy Lock/Unlock supported bit 4 Queued Erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Page mode read supported bit 8 Synchronous read supported bit 9 Simultaneous operation supported bit 10 Extended flash Array Blocks supported bit 11 to 29 reserved; undefined bits are `0'. bit 30 CFI links to follow bit 31 Optional features. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field.
(P+8)h = 112h 0000h
No Yes Yes No No Yes Yes Yes Yes Yes Yes No No
Supported functions after suspend Read Array, Read Status Register and CFI query (P+9)h = 113h 0001h bit 0 Program supported after erase suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' (P+A)h = 114h 0033h Block protect status Defines which bits in the block status register section of the query are implemented. bit 0 Block protect status register lock/unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock status register Lock-Down bit active (1 = Yes, 0 = No) (P+B)h = 115h 0000h bit 4 EFA Block protect status register Lock/Unlock bit active (1=yes, 2=No) bit 5 EFA Block Lock status register Lock-Down bit active (1=yes, 2=No) bit 15 to 6 and 3 to 2 Reserved for future use; undefined bits are `0' VDD logic supply optimum program/erase voltage (highest performance) (P+C)h = 116h 0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV (P+D)h = 117h 0090h VPP supply optimum program/erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV
Yes
Yes Yes Yes Yes
1.8 V
9V
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M58PR512LE, M58PR001LE Table 46.
Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h
Common flash interface
Protection Register information
Data 0002h 0080h 0000h 0003h 0003h 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h Protection Register 2: protection description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection field 1: protection description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Value 2 80h 00h 8 bytes 8 bytes 89h 00h 00h 00h 0 0 0 16 0 16
Table 47.
Offset
Burst Read information
Data Description Value
Page-mode read capability n (P+1D)h = 127h 0005h bits 0-7 'n' such that 2 HEX value represents the number of readpage bytes. See offset 0028h for device word width to determine page-mode data output width. (P+1E)h = 128h 0003h Number of synchronous mode read configuration fields that follow.
32 bytes
3
Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates (P+1F)h = 129h 0002h that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. (P+20)h = 12Ah 0003h Synchronous mode read capability configuration 2 (P-21)h = 12Bh 0007h Synchronous mode read capability configuration 3
8
16 Cont.
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Common flash interface Table 48. Bank and erase block region information
Data 01h
M58PR512LE, M58PR001LE
Offset(1) (P+22)h = 12Ch
Description Number of bank regions within the device(2)
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There is one bank region, see tables 37, 38, 39 and 40 in Appendix A.
Table 49.
Offset
Bank and erase block region 1 information(1)
Data 16h 00h 08h Number of identical banks within bank region 1 00h 11h Number of program or erase operations allowed in bank region 1: Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is being erased Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is being erased Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2) Description Data size of this bank region information section (addressable locations including this one)
(P+23)h = 12Dh (P+24)h = 12Eh (P+25)h = 12Fh (P+26)h = 130h (P+27)h = 131h
(P+28)h = 132h
00h
(P+29)h = 133h
00h
(P+2A)h = 134h
01h
(P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h (P+30)h = 13Ah
1Fh(3) 3Fh(4) 00h 00h 04h 64h 00h
Bank region 1 Erase block type 1 information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: nx256 = number of bytes in erase block region
Bank region 1 (Erase block type 1) Minimum block erase cycles x 1000 Bank region 1 (Erase block type 1): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" Bits 5-7: reserved
(P+31)h = 13Bh
12h
102/123
M58PR512LE, M58PR001LE Table 49.
Offset
Common flash interface
Bank and erase block region 1 information(1) (continued)
Data Description Bank region 1 (Erase block type 1): Page mode and Synchronous mode capabilities Bit 0: page-mode reads permitted Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved Bank region 1 (Erase block type 1) programming region information Bit 0-7: aligned size of programming region in bytes Bit 8-14: reserved Bit 15: Legacy flash operation (ignore bit 0-7) Bit 16-23: Control mode valid size in bytes Bit 24-31: reserved Bit 32-39: Control mode invalid size in bytes Bit 40-46: reserved Bit 47: Legacy flash operation (ignore bit 16-23 and 32-39)
(P+32)h = 13Ch
03h
(P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h (P+38)h = 142h
0Ah 00h 10h 00h 10h 00h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There is one bank region, see tables 37, 38, 39 and 40 in Appendix A. 3. Applies to M58PR512LE. 4. Applies to M58PR001LE.
Table 50.
Extended flash array bank and erase block region information
Data 01h Description Number of bank regions within the device(2)
Offset (1) (P+39)h = 143h
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There is one EFA bank region.
103/123
Common flash interface Table 51.
Offset
(1)
M58PR512LE, M58PR001LE
Extended flash array bank and erase block region 1 information
Data 16h 00h 01h Number of identical banks within bank region 1 00h 11h Number of program or erase operations allowed in bank region 1: Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is being erased Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is being erased Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations Types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2). Bank region 1 Erase block type 1 information Bits 0-15: n+1 = number of identical-sized erase blocks in each bank Bits 16-31: nx256 = number of bytes in erase block region Description Data size of this bank region information section (addressable locations including this one)
(P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h (P+3E)h = 148h
(P+3F)h = 149h
00h
(P+40)h = 14Ah
00h
(P+41)h = 14Bh
01h
(P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh (P+46)h = 150h (P+47)h = 151h
03h 00h 20h 00h 64h 00h Bank region 1 (Erase block type 1) Minimum block erase cycles x 1000 Bank region 1 (Erase block type 1): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for internal ECC used BIts 5-7: reserved Bank region 1 (Erase block type 1): page mode and synchronous mode capabilities Bit 0: page-mode reads permitted Bit 1: synchronous reads permitted Bit 2: synchronous writes permitted Bits 3-7: reserved
(P+48)h = 152h
01h
(P+49)h = 153h
03h
104/123
M58PR512LE, M58PR001LE Table 51.
Offset(1) (P+4A)h = 154h (P+4B)h = 155h (P+4C)h = 156h (P+4D)h = 157h (P+4E)h = 158h (P+4F)h = 159h
Common flash interface
Extended flash array bank and erase block region 1 information
Data 00h 80h 00h 00h 00h 80h Description Bank region 1 (Erase block type 1) programming region information Bit 0-7: aligned size of programming region in bytes Bit 8-14: reserved Bit 15: legacy flash operation (ignore bit 0-7) Bit 16-23: control mode valid size in bytes Bit 24-31: reserved Bit 32-39: control mode invalid size in bytes Bit 40-46: reserved Bit 47: legacy flash operation (ignore bit 16-23 and 32-39)
1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There is one EFA bank region.
105/123
Flowcharts and pseudocodes
M58PR512LE, M58PR001LE
Appendix C
Flowcharts and pseudocodes
Figure 24. Program and EFA block program flowchart and pseudocode
program_command (addressToProgram, dataToProgram) /* EFA_program_command (addressToProgram, dataToProgram) */ { writeToFlash (addressToProgram, 0x41); /*writeToFlash (addressToProgram, 0x44);*/ /* 41h is the command for program array, while 44h is the command for program EFA block */ /*see note (1)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); /* see note (3)*/ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (2, 3) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (2, 3) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (2, 3) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
Start
Write 41h (Main Array) or 44h (EFA) (1)
Write Address & Data
Read Status Register (3)
SR7 = 1
AI10515
1. Any address within the 'A' segment halves (A3=0) in a 1 Kbyte program region configured in control program mode. If a Program command is issued to a program region configured in the Object Program mode, SR4 and SR8 are set. 2. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program operation or after a sequence. 3. If an error is found, the status register must be cleared before further Program/Erase controller operations.
106/123
M58PR512LE, M58PR001LE Figure 25. Buffer program flowchart and pseudocode
Start Read Status Register 70h command, at Bank Address
Flowcharts and pseudocodes
Buffer_Program_command (Start_Address, n, buffer_Program[] ) /*The start address must be aligned to a 1KB boundary buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ {
SR7 = 1 YES
NO
status_register=readFlash (Bank_Address); } while (status_register.SR7==0);
Buffer Program E9h command, Block Address
do {writeToFlash (Block_Address, 0xE9) ;
Write n(1), Start Address
writeToFlash (Start_Address, n);
Write Buffer Data, Start Address
writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/
X=0
x = 0;
X=n NO
YES
while (xWrite Next Buffer Data, Next Program Address(2)
{ writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data);
x++; X=X+1 } Program Buffer to Flash Confirm D0h
writeToFlash (Start_Address, 0xD0);
Read Status Register
do {status_register=readFlash (Start_Address);
SR7 = 1 YES Full Status Register Check(3)
NO
} while (status_register.SR7==0);
full_status_register_check(); }
End
AI10516b
1. n + 1 is the number of data being programmed. The maximum buffer count is 1FF (512 words). 2. Next Program data is an element belonging to buffer_Program[].data; Next Program address is an element belonging to buffer_Program[].address. In a program region configured in Control Program mode buffer_Program[].data = FFFFh if A3 = 1. 3. Routine for error check by reading SR3, SR4 and SR1.
107/123
Flowcharts and pseudocodes
M58PR512LE, M58PR001LE
Figure 26. Program suspend and resume flowchart and pseudocode
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ;
Write FFh
YES Write FFh
Read Data
Read data from another address
read_data ( ); /*read data from another address*/
Write D0h
writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/
Write 70h(1) } Program Continues with Bank in Read Status Register Mode }
writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */
AI10117b
1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.
108/123
M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 27. Block erase and EFA block erase flowchart and pseudocode
erase_command ( blockToErase ) /* EFA_erase_command (blockToErase) { */ writeToFlash (blockToErase, 0x20) ; /* writeToFlash (blockToErase, 0x24) */ /* 20h is the command for Block Erase while 24h is the command for Erase EFA Block*/ /*see note (1) */ writeToFlash (blockToErase, 0xD0) ; /* only A12-Amax are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase) ; /* see note (1) */ /* E or G must be toggled*/
Start
Write 20h (Main Array) or 24h (EFA) (1)
Write Block Address & D0h
Read Status Register (1)
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (2) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (2) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI12858
1. Any address within the bank can equally be used. 2. If an error is found, the status register must be cleared before further program/erase operations.
109/123
Flowcharts and pseudocodes Figure 28. Erase suspend and resume flowchart and pseudocode
M58PR512LE, M58PR001LE
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
Write FFh
Read Data YES Write FFh Read data from another block or Program/Set Configuration Register or Block Lock/Unlock/Lock-Down Write D0h else }
read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/
{ writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another block*/
writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ writeToFlash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } }
Write 70h(1)
Erase continues with bank in Read Status Register mode
AI10116c
1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.
110/123
M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 29. Main array and EFA locking operations flowchart and pseudocode
locking_operation_command (address, lock_operation) { /* EFA_locking_operation_command (address, lock_operation) { */ writeToFlash (address, 0x60) ; /*configuration setup*/ /* writeToFlash (address, 0x64) */ /* 60h is the command for Locking Operations on the array while 64h is the command for Locking Operations on the EFA */ /* see note (1) */ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */
Start
Write 60h (Main Array) or 64h (EFA) (1)
Write 01h, D0h or 2Fh
Write 90h (1)
Read Block Lock States
Locking change confirmed? YES Write FFh (1)
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ }
End
AI10518
1. Any address within the bank can equally be used.
111/123
Flowcharts and pseudocodes Figure 30. Blank check flowchart and pseudocode
Start
M58PR512LE, M58PR001LE
blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC);
Write Block Address & D0h
writeToFlash (blockToCheck, 0xD0); /* Memory enters read status state after the Blank Check Command */
do { Read Status Register (1) status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR3 = 0 NO VPP Invalid Error (2) NO if (status_register.SR3==1) /* VPP invalid error */ error_handler () ; if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ;
SR4 = 1 SR5 = 1
YES
Command Sequence Error (2)
if (status_register.SR5==1) /* erase error */ error_handler () ; if (status_register.SR1==1) /* protected block error */ error_handler () ; }
SR5 = 0
NO
Erase Error (2)
SR1 = 0
NO
Protected Block Error (2)
End
ai10520
1. Any address within the bank can equally be used. 2. If an error is found, the status register must be cleared before further program/erase operations.
112/123
M58PR512LE, M58PR001LE
Flowcharts and pseudocodes
Figure 31. Protection Register program flowchart and pseudocode
Start
Write C0h (1)
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (1) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (1) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ;
Write Address & Data
Read Status Register (1)
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO
VPP Invalid Error (2, 3)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (2, 3)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (2, 3)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177c
1. Status check of SR1 (protected block), SR3 (VPP invalid) and SR4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the status register must be cleared before further Program/Erase controller operations.
113/123
Flowcharts and pseudocodes
M58PR512LE, M58PR001LE
Figure 32. Buffer enhanced factory program flowchart and pseudocode
Start Write 80h to Address WA1 SETUP PHASE
Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) {
writeToFlash (start_address, 0x80) ;
Write D0h to Address WA1
writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address);
Read Status Register
NO
SR7 = 0 YES
NO
SR4 = 1
Initialize count X=0 Write PDX (1) Address WA1
if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Locked Block */ } PROGRAM AND while (status_register.SR7==1) VERIFY PHASE x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]);
Read Status Register SR3 and SR1for errors
Exit
Increment Count X=X+1
x++;
NO
X = 512 YES Read Status Register
}while (x<512) do {
status_register = readFlash (start_address);
NO
SR0 = 0 YES
}while (status_register.SR0==1)
NO
Last data? YES
} while (not last data)
Write FFFFh to Address = NOT BA1 (2)
writeToFlash (another_block_address, FFFFh)
EXIT PHASE
Read Status Register
do { status_register = readFlash (start_address)
NO
SR7 = 1 YES Full Status Register Check End
}while (status_register.SR7==0)
full_status_register_check();
}
AI10519b
1. When programming a program region configured in Control Program mode, 'B' half segment addresses (A3 = 1) should not contain '0' values. 2. BA1 = block containing start address WA1.
114/123
M58PR512LE, M58PR001LE
Command interface state tables
Appendix D
Table 52.
Command interface state tables
Command interface states - modify table, next state 1
command input to chip and resulting chip next state (7) EFA Read Program Program EFA Setup Setup 94h 41h pgrm setup 44h EFA block pgrm setup Block Erase Setup 20h erase setup EFA Block Erase Setup 24h EFA block erase setup Program/ Erase Suspend B0h
Current chip state
Read Array
BP
BEFP
Confirm, Resume
Read Status
FFh
E9h(8,9,10)
80h BEFP setup
D0h
70h
ready Lock/CR/ECR Setup
ready
BP setup
ready
ready (sequence error) Lock EFA Block Setup setup OTP busy IS in OTP busy setup busy WP or IS in program EFA busy Block WP suspend IS in PS setup
(1), (2) (2)
ready (unlock) OTP busy
ready (sequence error)
OTP busy
IS in OTP busy
OTP busy
IS in OTP busy OTP busy WP busy
OTP busy
program busy
IS in program busy
pgrm busy
IS in program busy WP busy
program busy
WP WP busy suspend
PS
IS in PS
pgrm suspend
IS in PS WP suspend
program busy
WP suspend
BP load 1 (give word count load (N-1)) if N=0 go to BP confirm else go to BP load 2 (data load) (4) BP confirm when count =0 else BP load 2 ready (sequence error) BP busy IS in BP busy BP busy IS in BP busy BP busy BP suspend IS in BP suspend BP suspend IS in BP suspend BP suspend ready (sequence error) erase busy IS in erase busy erase busy Is in erase busy erase busy ES WP EFA block BP setup in setup in WP in ES ES ES ES IS in ES erase busy ES erase busy erase busy ready (sequence error) ES erase busy BP busy BP suspend BP busy (3) BP busy ready (sequence error) BP suspend BP busy
BP load 1
BP load 2 (2) BP confirm BP BP busy IS in BP busy BP suspend IS in BP suspend setup busy Erase or EFA IS in erase busy Block Erase suspend IS in ES
115/123
Command interface state tables Table 52.
M58PR512LE, M58PR001LE
Command interface states - modify table, next state 1 (continued)
command input to chip and resulting chip next state (7) EFA Read Program Program EFA Setup Setup 94h 41h 44h Block Erase Setup 20h EFA Block Erase Setup 24h Program/ Erase Suspend B0h
Current chip state
Read Array
BP
BEFP
Confirm, Resume
Read Status
FFh setup busy WP in ES or EFA IS in program Block WP busy in ES in ES suspend IS in PS in ES setup
(1) (2) (2)
E9h(8,9,10)
80h
D0h
70h
WB busy in ES WP busy in ES IS in program busy WP busy in in ES ES IS in program busy in ES WP WP busy in WP busy suspend ES in ES is ES
WP busy in ES WP suspend in ES IS in PS in ES WP suspend in ES IS in PS in ES WP busy in ES WP suspend is ES
WP suspend in ES BP load 1 in ES (give word count load (N-1)) if N=0 go to BP confirm in ES else go to BP load 2 in ES (data load) (4) BP confirm in ES when count = 0 else BP load 2 in ES ES (sequence error) BP busy in ES BP busy in ES (sequence error) ES (3) IS in BP busy in ES BP BP busy in suspend ES in ES BP busy in ES
BP load 1
BP load 2 (2) BP confirm
BP in ES BP busy IS in BP busy in ES BP suspend IS in BP suspend in ES Lock/CR/ECR/Lock EFA block setup in ES setup Blank Check blank check busy IS in blank check busy setup
BP busy in ES
IS in BP busy in ES
BP busy in ES BP suspend in IS in BP suspend in BP suspend ES ES suspend in ES IS in BP suspend in ES BP busy in ES BP suspend in ES
BP suspend in ES ES (sequence error) ready (sequence error) BC busy IS in BC busy BC busy IS in BC busy BC busy BEFP loading data ready (sequence error) ES (unlock ES (sequence error) block) blank check busy ready (sequence error) BC busy
BEFP mode
ready (sequence error)
BEFP Busy (5) (6) BEFP program and verify busy (in block address given matches on BEFP setup command). Commands treated as data
116/123
M58PR512LE, M58PR001LE Table 53.
Command interface state tables
Command interface states - modify table, next state 2
command input to chip and resulting chip next state Lock, CR, Lock EFA ECR Setup Setup 60h lock/CR/E CR setup 64h lock EFA block setup Blank Check Setup BCh blank check setup Block Lock Confirm 01h Lockdown Confirm 2Fh ready ready (lock) ready (sequence error) ready (EFA lock) OTP busy OTP busy IS in OTP busy OTP busy WP busy WP busy IS in program busy IS WP busy WP suspend WP (error bits suspend cleared) WP busy WP busy N/A ready IS ready OTP busy IS ready ready (set CR) Write CR/ECR Confirm 03h 04h Illegal Cmd or BEFP Data others ready
Current chip state
Clear SR Read ID
OTP Setup
WSM Operation Complete
50h ready
90h 98h ready
C0h OTP setup
Lock/CR/ECR Setup
Lock EFA Block Setup setup OTP busy IS in OTP busy setup busy WP or EFA Block WP IS in program busy
ready (lock down)
ready (sequence ready error) (sequence error)
N/A
suspend
IS in PS
WP suspend N/A WP suspend
IS in PS setup BP load 1
BP load 1 (give word count load (N-1)) if N=0 go to BP confirm else go to BP load 2 (data load) BP confirm when count = 0 else BP load 2 N/A
BP load 2
BP confirm when count =0 else BP load 2
BP confirm BP BP busy IS in BP busy BP suspend BP (error bits suspend cleared) BP busy
ready (sequence error) IS in BP busy IS BP busy BP busy ready IS ready
BP suspend
IS in BP suspend
BP suspend N/A BP suspend
IS in BP suspend setup busy IS in erase Erase or busy EFA Block Erase suspend erase busy
ready (sequence error) IS in erase busy IS erase busy ES (error bits cleared) lock EFA Lock/CR/E block CR setup setup in in ES ES erase busy
N/A ready IS nonready
ES
IS
ES N/A ES
IS in ES
117/123
Command interface state tables Table 53.
M58PR512LE, M58PR001LE
Command interface states - modify table, next state 2 (continued)
command input to chip and resulting chip next state Lock, CR, Lock EFA ECR Setup Setup 60h 64h Blank Check Setup BCh Block Lock Confirm 01h Lockdown Confirm 2Fh Write CR/ECR Confirm 03h 04h Illegal Cmd or BEFP Data others N/A WP busy in ES WP busy in ES ES IS in ES
Current chip state
Clear SR Read ID
OTP Setup
WSM Operation Complete
50h setup busy IS in program busy in ES
90h 98h
C0h
WP busy in ES WP busy in ES IS WP busy in ES WP suspend is WP ES (error suspend bits in ES cleared)
WP in ES or EFA Block WP in ES
suspend
IS in WP suspend in ES
WP suspend in ES N/A
IS in PS in ES setup BP load 1
WP suspend in ES BP load 1 in ES (give word count load (N-1)) if N=0 go to BP confirm in ES else go to BP load 2 in ES (data load)
WP suspend in ES
BP load 2
BP confirm in ES when count = 0 else BP load 2 in ES
BP confirm when count = 0 else BP load 2
N/A
BP confirm BP in ES BP busy IS in BP busy in ES BP suspend in BP BP suspend ES (error suspend bits is ES cleared) IS in BP suspend in ES Lock/CR/ECR setup in ES BP busy in ES
ready (sequence error) in ES IS in BP busy in ES IS BP busy in ES BP busy in ES ES IS in ES
IS in BP suspend in ES
BP suspend in ES N/A
BP suspend in ES
BP suspend in ES ES
ES (sequence error) Lock EFA block setup in ES setup Blank Check blank check busy IS in blank check busy setup BEFP Mode BEFP Busy BC busy ready (sequence error) IS in BC busy BC busy IS
ES (lock block)
ES (lock down)
ES (sequence error)
ES (lock error) N/A ready (error)
BC busy BC busy
ready IS ready N/A BEFP busy ready
ready (sequence error) BEFP program and verify busy (in block address given matches on BEFP setup command). Commands treated as data
118/123
M58PR512LE, M58PR001LE Table 54.
Command interface state tables
Command interface states - modify table, next output 1
command input to chip and resulting chip next state Read EFA Block 94h EFA Block Erase Setup 24h Program/ Erase Suspend B0h
Current chip state
Read Array
WP
EFA WP
BP
Erase Setup
BEFP Setup
Confirm, Resume
Read Status
FFh BEFP Setup, BEFP program and verify busy, Erase Setup, Erase EFA setup OTP Setup, BP Confirm, WP setup, WP setup in ES, BP confirm in ES, blank check setup EFA block WP setup, EFA block program setup in ES Lock/CR/ECR setup, Lock/CR/ECR setup in ES EFA block lock setup, EFA block lock setup in ES OTP busy ready, ES, BP suspend, WP busy, erase busy, BP busy, BP busy in ES, WP suspend, WP busy in ES, PS in ES, BP suspend in ES, Blank Check busy BP setup, BP load 1, BP load 2, IS
41h
44h
E9h
20h
80h
D0h
70h
status read
EFA block status read
status read
EFA block status read
read array
read EFA blocks
status read
EFA block status read
output state does not change
status read
EFA block status read
status read
output state does not change
status read
output state does not change
119/123
Command interface state tables Table 55. Command interface states - modify table, next output 2
M58PR512LE, M58PR001LE
command input to chip and resulting chip next state Lock, CR, ECR Setup 60h Lock EFA Setup 64h Lockdown Confirm 2Fh Write CR/ ECR Confirm 03h 04h Illegal cmd or BEFP Data others
Current Chip State
Clear SR
Read ID
Blank Check
OTP Setup
Lock Confirm
50h BEFP Setup, BEFP program and verify busy, Erase Setup, Erase EFA setup OTP Setup, BP Confirm, WP setup, WP setup in ES, BP confirm in ES, blank check setup EFA block WP setup, EFA block program setup in ES Lock/CR/ECR setup, Lock/CR/ECR setup in ES EFA block lock setup, EFA block lock setup in ES OTP busy ready, ES, BP suspend, WP busy, erase busy, BP busy, blank check busy, BP busy in ES, WP suspend, WP busy in ES, PS in ES, BP suspend in ES BP setup, BP load 1, BP load 2, IS output state does not change
90h 98h
BCh
C0h
01h
status read
EFA block status read array read array read status read EFA block status read
status read
EFA block status read
ID read
status read
EFA block status read
status read
output state does not change
output state does not change
output state does not change
Note:
1
WP = Word Program, BP = Buffer program, cmd = command, SR = status register, pgrm = program, IS = Illegal state, PS = Program suspend, ES = Erase suspend, CI = Command Interface, CR = configuration register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller, WA0 = Address in a block different from first BEFP address, ECR = enhanced configuration register. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read status register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. At Power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank results in undetermined data output. The Clear Status Register command clears the status register error bits except when the P/EC is busy or suspended. BEFP is allowed only when status register bit SR0 is reset to `0'. BEFP is busy if the block address is the first BEFP address. Any other commands are treated as data.
2
3 4 5
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M58PR512LE, M58PR001LE 6 7 8 9 10
Command interface state tables
BEFP aborts when the block address is different from the first block address and data are FFFFh. BEFP Exit when block address is different from first block address and data are FFFFh. During BP setup, while entering the number of words to be programmed and filling the buffer, the read status of the partition does not change. The BP confirm command changes the read status of the partition to Status Read. Illegal commands are commands not defined in the command set.
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Revision history
M58PR512LE, M58PR001LE
18
Revision history
Table 56.
Date 28-Apr-2006
Document revision history
Revision 0.1 Initial release. 1Gb density (M58PR001LE part number) added. VPP range for application environment changed in Table 24: Operating and AC measurement conditions. IPP1 unit changed in Table 26: DC characteristics - currents. Document status promoted from Target Specification to Preliminary Data. Address lines modified in Figure 13: Asynchronous page read AC waveforms. VPP max value modified in Table 23: Absolute maximum ratings. Small text changes. Modified Section 4.18: Set Enhanced Configuration Register command and Section 4.22: Suspend EFA Block command. Updated Table 22: Program/erase times and endurance cycles, Table 23: Absolute maximum ratings, Table 26: DC characteristics currents, Table 28: Asynchronous read AC characteristics, and Table 30: Write AC characteristics, write enable controlled. Added tLLTV timing in Table 29: Synchronous read AC characteristics and Figure 15: Single synchronous read AC waveforms. Modified Figure 28: Erase suspend and resume flowchart and pseudocode. Document status promoted from Preliminary Data to Datasheet. Added the TFBGA105 (ZAD) and TFBGA107 (ZAC) packages to the document, most specifically in Figure 2: TFBGA105 connections (top view through package), Figure 3: TFBGA107 connections (top view through package), Figure 22: TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline, Figure 23: TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package outline, Table 34: TFBGA105 9 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, mechanical data, and Table 35: Stacked TFBGA107 8 x 11 mm - 9 x 12 active ball array, 0.8 mm pitch, package mechanical data. Changed the maximum IDD7 value for "program/erase in one bank, asynchronous read in another bank" from 80 to 85. Removed the 256 Mbit density and all its associated data from the document. Applied the Numonyx branding. Changed all the IDD1, IDD2, IDD3, IDD4, IDD6, and IDD8 maximum values inTable 26. Changes
15-May-2006
0.2
14-Nov-2006
1
06-Sep-2007
2
19-Nov-2007
3
21-Mar-2008
4
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M58PR512LE, M58PR001LE
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